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2025-11-03drm/xe: Inline gt_reset in the workerLucas De Marchi1-18/+11
gt_reset() doesn't make sense by itself: it can only be called as part of the worker. Inline it there to avoid it being called from elsewhere and clarify the gt_reset() vs do_gt_reset() paths. Note that the error return from gt_reset() was just being ignored. Also add a comment to the xe_pm_runtime_put() to make sure the get()/put() pair is clear. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251031222244.37735-2-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-01drm/mediatek: Add pm_runtime support for GCE power controlJason-JH Lin1-0/+7
Call pm_runtime_resume_and_get() before accessing GCE hardware in mbox_send_message(), and invoke pm_runtime_put_autosuspend() in the cmdq callback to release the PM reference and start autosuspend for GCE. This ensures correct power management for the GCE device. Fixes: 8afe816b0c99 ("mailbox: mtk-cmdq-mailbox: Implement Runtime PM with autosuspend") Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20250829091727.3745415-3-jason-jh.lin@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2025-11-01drm/mediatek: Disable AFBC support on Mediatek DRM driverAriel D'Alessandro1-23/+1
Commit c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver") added AFBC support to Mediatek DRM and enabled the 32x8/split/sparse modifier. However, this is currently broken on Mediatek MT8188 (Genio 700 EVK platform); tested using upstream Kernel and Mesa (v25.2.1), AFBC is used by default since Mesa v25.0. Kernel trace reports vblank timeouts constantly, and the render is garbled: ``` [CRTC:62:crtc-0] vblank wait timed out WARNING: CPU: 7 PID: 70 at drivers/gpu/drm/drm_atomic_helper.c:1835 drm_atomic_helper_wait_for_vblanks.part.0+0x24c/0x27c [...] Hardware name: MediaTek Genio-700 EVK (DT) Workqueue: events_unbound commit_work pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : drm_atomic_helper_wait_for_vblanks.part.0+0x24c/0x27c lr : drm_atomic_helper_wait_for_vblanks.part.0+0x24c/0x27c sp : ffff80008337bca0 x29: ffff80008337bcd0 x28: 0000000000000061 x27: 0000000000000000 x26: 0000000000000001 x25: 0000000000000000 x24: ffff0000c9dcc000 x23: 0000000000000001 x22: 0000000000000000 x21: ffff0000c66f2f80 x20: ffff0000c0d7d880 x19: 0000000000000000 x18: 000000000000000a x17: 000000040044ffff x16: 005000f2b5503510 x15: 0000000000000000 x14: 0000000000000000 x13: 74756f2064656d69 x12: 742074696177206b x11: 0000000000000058 x10: 0000000000000018 x9 : ffff800082396a70 x8 : 0000000000057fa8 x7 : 0000000000000cce x6 : ffff8000823eea70 x5 : ffff0001fef5f408 x4 : ffff80017ccee000 x3 : ffff0000c12cb480 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000c12cb480 Call trace: drm_atomic_helper_wait_for_vblanks.part.0+0x24c/0x27c (P) drm_atomic_helper_commit_tail_rpm+0x64/0x80 commit_tail+0xa4/0x1a4 commit_work+0x14/0x20 process_one_work+0x150/0x290 worker_thread+0x2d0/0x3ec kthread+0x12c/0x210 ret_from_fork+0x10/0x20 ---[ end trace 0000000000000000 ]--- ``` Until this gets fixed upstream, disable AFBC support on this platform, as it's currently broken with upstream Mesa. Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver") Cc: stable@vger.kernel.org Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20251024202756.811425-1-ariel.dalessandro@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2025-11-01Merge remote-tracking branch 'drm/drm-next' into msm-next-robclarkRob Clark1828-35388/+95305
Back-merge drm-next to get caught up. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-01drm/i915/ltphy: Modify the step that need to be skippedSuraj Kandpal1-30/+33
Bspec has changed the non tbt pll enable sequence now we skip steps 5-17 if no config change has occurred. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
2025-11-01drm/i915/display: Aux Enable and Display powerwell timeoutsSuraj Kandpal1-2/+20
From XE3P we can now poll if the AUX power is up or down define the timeouts for each respectively. Bspec: 68967 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-25-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal4-1/+63
Define function to verify the LT PHY PLL state function and call it in intel_modeset_verify_crtc. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-24-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define function to readout LT Phy PLL stateSuraj Kandpal3-0/+50
Define a function to readout hw state for LT Phy PLL which can be used in get_config function call. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal3-1/+68
Define function to compare the state and if mismatch is detected dump both the states. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-22-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal2-0/+91
We need to enable and disable the Tx for each active lane after the Non-TBT enable sequence is done. Bspec: 74500, 74497, 74701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-21-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal4-3/+88
Program LT Phy voltage swing using the Swing tables and plug in the function at encoder->set_signal_level Bspec: 74493 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com
2025-11-01drm/i915/ddi: Define LT Phy Swing tablesSuraj Kandpal2-1/+89
Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp. HDMI TMDS is not needed since LT Phy H/w handles that. Bspec: 74493 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-19-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal5-4/+37
Hook up the LT Phy enable and disable sequences using encoder-> enable/disable_clock and reusing the TBT enable disable sequence from cx0 PHY since it remains the same. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal3-0/+80
Program in the steps for Non TBT PLL disable sequence. The whole function can be defined in one shot since most of prequiste functions are already coded in. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-17-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal3-2/+32
Program the rest of the LT Phy Non TBT PLL Enable sequence. This can be done in a single patch since the rest of the prequistie functions are already coded in. Bspec: 74492, 69701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal2-0/+26
Program the rest of the steps with regards to PORT_CLOCK_CTL in Non-TBT PLL enable sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal5-5/+143
Program the LT PHY P2P transaction which uses P2M cycle to get get data fro Phy when it is ready and then go read the MAC register from the MAC address space. Bspec: 68966, 74497, 74483, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal3-0/+97
Create a reverse algorithm which is used to find port clock from the LT PHY state is provided which is used for comparision & verification functions. Bspec: 74667 Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal1-0/+26
We enable SSC when we program PORT_CLOCK_CTL register. We logically determine if ssc is enabled or not while we calculate our state. Bspec: 74492, 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal1-0/+4
When we get the eDP tables we reuse dp tables for some data rates. We need to modify the 3rd config value of this table to 1 instead of 0 since that is the only difference in the dp and edp table for that particular data rate. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-11-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal3-5/+45
Fetch the tables which need to be used and program it in the specified VDR register space. Everything is done over the respective lanes. Bspec: 68862, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal4-1/+1036
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a function to use the correct table. Bspec: 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal3-25/+123
Read PHY_VDR_0_CONFIG to check if there is any change in the register and decide based on that if P2P sequence to change the data rate of LT PHY are required or not. This scenario only happens if the requested mode uses 1.62Gbps with DP mode since LT PHY defaults to this mode if any other mode is requested we need to follow the whole sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal3-3/+18
Add a wrapper on cx0 powerdown change sequence for LT Phy usage, as the sequence remains unchanged when going from SNPS Phy to LT Phy. Bspec: 74495 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal2-0/+38
Program sequence from port clock ctl except for the SSC enablement part which will be taken care of later. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal3-18/+18
Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and make it non static. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal8-1/+202
Define function to bring phy lane out of reset for LT Phy and the corresponding pre-requisite steps before we follow the steps for Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence function in which we can place this function Bspec: 77449, 74749, 74499, 74495, 68960 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal2-12/+12
Change the register bit naming for powerdown values from CX0 to XELPDP so that it can be used with LT Phy too. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-3-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy related VDR and Pipe RegistersSuraj Kandpal1-0/+24
Add LT Phy related VDR and pipe registers into its own new file. Bspec: 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
2025-11-01Merge tag 'amd-drm-next-6.19-2025-10-29' of ↵Simona Vetter256-892/+3549
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License copy-pasta fixes - HDP eDP panel fix - Vblank fix - RAS fixes - SR-IOV updates - SMU 13 VCN reset fix - DMUB fixes - DC frame limit fix - Additional DC underflow logging - DCN 3.1.5 fixes - DC Analog encoders support - Enable DC on bonaire by default - UserQ fixes - Remove redundant pm_runtime_mark_last_busy() calls amdkfd: - Process cleanup fix - Misc fixes radeon: - devm migration fixes - Remove redundant pm_runtime_mark_last_busy() calls UAPI - Add ABM KMS property Proposed kwin changes: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029205713.9480-1-alexander.deucher@amd.com
2025-10-31drm/xe/pf: Allow to stop the VF using sysfsMichal Wajdeczko1-0/+49
It is expected that VFs activity will be monitored and in some cases admin might want to silence specific VF without killing the VM where it was attached. Add write-only attribute to stop GuC scheduling at VFs level. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── vf1/ │ └── stop [WO] bool ├── vf2/ │ └── stop [WO] bool Writing "1" or "y" (or whatever is recognized by the strtobool() function) to this file will trigger the change of the VF state to STOP (GuC will stop servicing the VF). To go back to a READY state (to allow GuC to service this VF again) the VF FLR must be triggered (which can be done by writing 1 to device/reset file). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-17-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add sysfs device symlinks to enabled VFsMichal Wajdeczko3-0/+101
For convenience, for every enabled VF add 'device' symlink from our SR-IOV admin VF folder to enabled sysfs PCI VF device entry. Remove all those links when disabling PCI VFs. For completeness, add static 'device' symlink for the PF itself. /sys/bus/pci/drivers/xe/BDF/sriov_admin/ ├── pf │   └── device -> ../../../BDF # PF BDF ├── vf1 │   └── device -> ../../../BDF' # VF1 BDF ├── vf2 │   └── device -> ../../../BDF" # VF2 BDF Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-16-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Promote xe_pci_sriov_get_vf_pdevMichal Wajdeczko2-13/+24
In the upcoming patch we would like to use this private helper during preparation of the sysfs links. Promote it. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-15-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF scheduling priority using sysfsMichal Wajdeczko1-2/+82
We have just added bulk change of the scheduling priority for all VFs and PF, but that only allow to select LOW and NORMAL priority. Add read-write attribute under PF to allow changing its priority without impacting other VFs priority settings. For completeness also add read-only attributes under VFs, to show currently selected priority levels used by the VFs. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ └── sched_priority [RW] low, normal, high ├── vf1/ │ └── profile │ └── sched_priority [RO] low, normal Writing "high" to the PF read-write attribute will change PF priority on all tiles/GTs to HIGH (schedule function in the next time-slice after current one completes and it has work). Writing "low" or "normal" to change priority to LOW/NORMAL is supported. When read, those files will display the current and available scheduling priorities. The currently active priority level will be enclosed in square brackets, default output will be like: $ grep . -h sriov_admin/{pf,vf1,vf2}/profile/sched_priority [low] normal high [low] normal [low] normal Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-14-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs priority using sysfsMichal Wajdeczko1-1/+41
It is expected to be a common practice to configure the same level of scheduling priority across all VFs and PF (at least as starting point). Due to current GuC FW limitations it is also the only way to change VFs priority. Add write-only sysfs attribute that will apply required priority level to all VFs and PF at once. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   └── sched_priority [WO] low, normal Writing "low" to this write-only attribute will change PF and VFs scheduling priority on all tiles/GTs to LOW (function will be scheduled only if it has work submitted). Similarly, writing "normal" will change functions priority to NORMAL (functions will be scheduled irrespective of whether there is a work or not). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-13-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to provision scheduling priorityMichal Wajdeczko2-0/+97
We already have function to configure PF (or VF) scheduling priority on a single GT, but we also need function that will cover all tiles and GTs. However, due to the current GuC FW limitation, we can't always rely on per-GT function as it actually only works for the PF case. The only way to change VFs scheduling priority is to use 'sched_if_idle' policy KLV that will change priorities for all VFs (and the PF). We will use these new functions in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-12-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow bulk change all VFs EQ/PT using sysfsMichal Wajdeczko1-0/+36
It is expected to be a common practice to configure the same values of execution quantum and preemption timeout parameters across all VFs. Add write-only sysfs attributes that will apply required EQ/PT values globally, without forcing admin to update PF and each VF separately. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── .bulk_profile │   ├── exec_quantum_ms [WO] unsigned integer │   └── preempt_timeout_us [WO] unsigned integer Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-11-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk provision EQ/PTMichal Wajdeczko2-0/+58
We already have functions to configure EQ/PT for single VF across all tiles/GTs. Now add helper functions that will do that for all VFs (and the PF) at once. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-10-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add functions to bulk configure EQ/PT on GTMichal Wajdeczko2-0/+58
We already have functions to bulk configure 'hard' resources like GGTT, LMEM or GuC context/doorbells IDs. Now add functions for the 'soft' scheduling parameters, as we will need them soon in the upcoming patches. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-9-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Fix signature of internal config helpersMichal Wajdeczko1-2/+2
Both pf_get_exec_quantum() and pf_get_preempt_timeout() should return u32 as this is a type of the underlying data. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-8-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Relax report helper to accept PF in bulk configsMichal Wajdeczko1-5/+8
Our current bulk configuration requests are only about VFs, but we want to add new functions that will also include PF configs. Update our bulk report helper to accept also PFID as first VFID. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-7-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Allow change PF and VFs EQ/PT using sysfsMichal Wajdeczko3-2/+195
On current platforms, in SR-IOV virtualization, the GPU is shared between VFs on the time-slice basis. The 'execution quantum' (EQ) and 'preemption timeout' (PT) are two main scheduling parameters that could be set individually per each VF. Add EQ/PT read-write attributes for the PF and all VFs. By exposing those two parameters over sysfs, the admin can change their default values (infinity) and let the GuC scheduler enforce that settings. /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer ├── vf1/ │ └── profile │ ├── exec_quantum_ms [RW] unsigned integer │ └── preempt_timeout_us [RW] unsigned integer Writing 0 to these files will set infinity EQ/PT for the VF on all tiles/GTs. This is a default value. Writing non-zero integers to these files will change EQ/PT to new value (in their respective units: msec or usec). Reading from these files will return EQ/PT as previously set on all tiles/GTs. In case of inconsistent values detected, due to errors or low-level configuration done using debugfs, -EUCLEAN error will be returned. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-6-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF PT config functionsMichal Wajdeczko2-17/+52
In upcoming patches we will want to configure VF's preemption timeout (PT) on all GTs under single lock to avoid potential races due to parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-5-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Add _locked variants of the VF EQ config functionsMichal Wajdeczko2-17/+53
In upcoming patches we will want to configure VF's execution quantum (EQ) on all GTs under single lock to avoid potential races in parallel GT configuration attempts. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251030222348.186658-4-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Take RPM during calls to SR-IOV attr.store()Michal Wajdeczko1-2/+14
We expect that all SR-IOV attr.store() handlers will require active runtime PM reference. To simplify implementation of those handlers, take an implicit RPM reference on their behalf. Also wait until PF completes its restart. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-3-michal.wajdeczko@intel.com
2025-10-31drm/xe/pf: Prepare sysfs for SR-IOV admin attributesMichal Wajdeczko5-0/+317
We already have some SR-IOV specific knobs exposed as debugfs files to allow low level tuning of the SR-IOV configurations, but those files are mainly for the use by the developers and debugfs might not be available on the production builds. Start building dedicated sysfs sub-tree under xe device, where in upcoming patches we will add selected attributes that will help provision and manage PF and all VFs: /sys/bus/pci/drivers/xe/BDF/ ├── sriov_admin/ ├── pf/ ├── vf1/ ├── vf2/ : └── vfN/ Add all required data types and helper macros that will be used by upcoming patches to define actual attributes. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251030222348.186658-2-michal.wajdeczko@intel.com
2025-10-31Merge tag 'drm-xe-fixes-2025-10-30' of ↵Simona Vetter2-11/+16
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Fix xe_validation_guard() not guarding (Thomas Hellström) - Do not wake device during a GT reset (Matthew Brost) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/o2b3lucyitafbbcd5bewpfqnslavtnnpc6ck4qatnou2wwukix@rz6seyfw75uy
2025-10-31Merge tag 'drm-misc-fixes-2025-10-30' of ↵Simona Vetter8-22/+43
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: ast: - Preserve correct bits on register I/O dma-fence: - Use correct timeline name etnaviv: - Use correct GPU adress space for flush imx: - parallel-display: Fix bridge handling nouveau: - Fix locking in scheduler panel: - kingdisplay-kd097d04: Disable EOT packet - sitronix-st7789v: Use correct SYNC flags sched: - Fix locking to avoid race condition - Fix SIGKILL handling sysfb: - Avoid NULL-pointer access Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251030195644.GA188441@localhost.localdomain
2025-10-31Merge tag 'drm-intel-fixes-2025-10-30' of ↵Simona Vetter1-1/+54
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes - Fix DMC/DC6 asserts on ADL-S (Ville) Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aQNtTV75vPaDhnXh@intel.com
2025-10-31Merge tag 'drm-msm-fixes-2025-10-29' of ↵Simona Vetter15-43/+59
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.18-rc4 CI - Disable broken sanity job GEM - Fix vm_bind prealloc error path - Fix dma-buf import free - Fix last-fence update - Reject MAP_NULL if PRR is unsupported - Ensure vm is created in VM_BIND ioctl GPU - GMU fw parsing fix DPU: - Fixed mode_valid callback - Fixed planes on DPU 1.x devices. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV03kUm1ms7FBg0m9U4ZcyickSWbnayAWqYqs0XH4UjWf+A@mail.gmail.com
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