summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Collapse)AuthorFilesLines
2025-05-26drm/ttm: make ttm_bo_get internalChristian König1-0/+10
Prevent drivers from using this directly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Simona Vetter <simona.vetter@ffwll.ch> Link: https://lore.kernel.org/r/20240723121750.2086-8-christian.koenig@amd.com
2025-05-26drm/ttm: revert "Export ttm_bo_get_unless_zero()"Christian König4-0/+52
This reverts commit 24dc64c1ba5c3ef0463d59fef6df09336754188d. Shouldn't be needed by drivers any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Reviewed-by: Simona Vetter <simona.vetter@ffwll.ch> Link: https://lore.kernel.org/r/20240723121750.2086-6-christian.koenig@amd.com
2025-05-26drm/i915/dp: Fix the enabling/disabling of audio SDP splittingImre Deak4-16/+17
Adjust the enabling/disabling steps of the DP audio SDP splitting according to a recent Bspec update. This moves the enabling to the audio codec enable sequence after the transcoder is enabled and disables SDP splitting explicitly during the audio disable sequence. Bspec requires waiting for a vblank event after the transcoder is enabled and before SDP splitting is enabled. There is no need for an explicit wait for this, since after the transcoder is enabled this vblank event is guaranteed to have happened via a flip done wait (see intel_atomic_commit_tail() -> drm_atomic_helper_wait_for_flip_done()). The bspec update is for LNL+ only, but the HW team clarified that this has been always the intended sequence on all platforms and bspec will be updated everywhere accordingly. The way SDP splitting was originally enabled matched the version of bspec at that time. Adding here the Fixes: line still, since this change fixes a FIFO underrun on PTL during output enabling when DSC is enabled. Bspec: 49283, 68943 Fixes: 8853750dbad8 ("drm/i915: Enable SDP split for DP2.0") Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250520142219.1688401-1-imre.deak@intel.com (cherry picked from commit 56764c845aa5be14cd53702fc9f2da23e25857de) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-26drm/i915: Disable updating of LUT values during vblankChaitanya Kumar Borah1-1/+4
Do not schedule vblank worker for LUT update if the registers are double buffered v2: Do not schedule the worker at all (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-12-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/color: Do not pre-load LUTs with DB registersChaitanya Kumar Borah1-0/+4
Since Double Buffered LUT registers can be written in active region no need to preload them. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-11-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915: Program DB LUT registers before vblankChaitanya Kumar Borah1-2/+8
Double Buffered LUT registers can be programmed in the active region. This patch implements the MMIO path for it. Program the registers after evading vblank. The HW latches on to the registers after delayed vblank. It takes around 1024 cdclk cycles(~one scanline) for this. Following assumptions have been made while making this change - Current vblank evasion time is sufficient for programming the LUT registers. - Current guardband calculation would be sufficient for the HW to latch on to the new values v2: move loading LUTs to commit_pipe_post_planes() since a vblank evasion failure for this is probably less drastic than for plane programming. (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-10-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/display: use GOSUB to program double buffered LUT registersChaitanya Kumar Borah4-19/+47
With addition of double buffered GAMMA registers in PTL, we can now program them in the active region. Use GOSUB instruction of DSB to program them. It is done in the following steps: 1. intel_color_prepare_commit() - If the platform supports, prepare a dsb instance (dsb_color) hooked to DSB0. - Add all the register write instructions to dsb_color through the load_lut() hook - Do not add the vrr_send_push() logic to the buffer as it should be taken care by dsb_commit instance of DSB0 - Finish preparation of the buffer by aligning it to 64 bit 2. intel_atomic_dsb_finish() - Add the gosub instruction into the dsb_commit instance of DSB0 using intel_dsb_gosub() - If needed, add the vrr_send_push() logic to dsb_commit after it v2: Refactor code to simplify commit completion flow. Add some helpers along the way (Ville) v3: s/doubled/double and add display to commit message prefix (Uma) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-9-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915: s/dsb_color_vblank/dsb_colorChaitanya Kumar Borah4-27/+27
With double buffer gamma registers in the mix, we need not wait for vblank to execute gamma writes through dsb. Before we implement that s/dsb_color_vblank/dsb_color. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-8-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: Add support for GOSUB interruptChaitanya Kumar Borah2-0/+11
DSB raises an interrupt when there is a nested GOSUB command or illegal Head/Tail. Add support to log such errors in the DSB interrupt handler. v2: Enable support only in platforms that support this (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-7-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: add intel_dsb_gosub_finish()Chaitanya Kumar Borah2-0/+14
A DSB buffer which will be used for GOSUB execution does not need the DEWAKE mechanism but still need to be 64 bit aligned. Add helper to finish preparation of a dsb buffer to be executed with GOSUB instruction. v2: Add a cacheline of noops at the end of GOSUB buffer (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-6-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: Implement intel_dsb_gosub()Ville Syrjälä2-0/+75
Add support for the new GOSUB DSB instruction (available on ptl+), which instructs the DSB to jump to a different buffer, execute the commands there, and then return execution to the next instruction in the original buffer. There are a few alignment related workarounds that need to be dealt with when emitting GOSUB instruction. v2: Right shift head and tail pointer passed to gosub command (chaitanya) v3: Add macro for right shifting head/tail pointers (Animesh) v4: Fix typo in commit message (Uma) Add comments explaining why right shifting htp is needed (Animesh) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-5-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: Extract intel_dsb_{head,tail}()Ville Syrjälä1-10/+14
Extract the code that calculates the DSB_HEAD/TAIL register values into small helpers. We already have two copies of this, and soon there will be a third. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-4-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: Extract assert_dsb_tail_is_aligned()Ville Syrjälä1-4/+15
Extract the DSB tail alignment checks into helper. We already have two uses of this, and soon we'll get a third. v2: s/soo/soon in commit message (Animesh) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-3-chaitanya.kumar.borah@intel.com
2025-05-26drm/i915/dsb: Extract intel_dsb_ins_align()Ville Syrjälä1-2/+14
Extract the code that alings the next instruction to the next QW boundary into a small helper. I'll have some more uses for this later. Also explain why we don't have to zero out the extra DW. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-2-chaitanya.kumar.borah@intel.com
2025-05-26drm/vesadrm: Use helpers for programming gamma rampsThomas Zimmermann1-64/+36
Replace vesadrm's code for programming the hardware gamma LUT with DRM helpers. Either load a provided gamma ramp or program a default. Set the individual entries with a callback. Each gamma value is given as 3 individual 16-bit values for red, green and blue. The driver reduces them to 8 bit to make them fit into hardware registers. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20250520094203.30545-6-tzimmermann@suse.de
2025-05-26drm/ofdrm: Use helpers for programming gamma rampsThomas Zimmermann1-50/+30
Replace ofdrm's code for programming the hardware gamma LUT with DRM helpers. Either load a provided gamma ramp or program a default. Set the individual entries with a callback. Each gamma value is given as 3 individual 16-bit values for red, green and blue. The driver reduces them to 8 bit to make them fit into hardware registers. v2: - fix coding style Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20250520094203.30545-5-tzimmermann@suse.de
2025-05-26drm/mgag200: Use helpers for programming gamma rampsThomas Zimmermann5-58/+44
Replace mgag200's code for programming the hardware gamma LUT with DRM helpers. Either load a provided gamma ramp or program a default. Set the individual entries with a callback. Each gamma value is given as 3 individual 16-bit values for red, green and blue. The driver reduces them to 8 bit to make them fit into hardware registers. v2: - fix coding style Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/20250520094203.30545-4-tzimmermann@suse.de
2025-05-26drm/ast: Use helpers for programming gamma ramps and palettesThomas Zimmermann1-27/+42
Replace ast's code for programming the hardware gamma/palette LUT with DRM helpers. Either load provided data or program a default. Set the individual entries with a callback. Each gamma/palette value is given as 3 individual 16-bit values for red, green and blue. The driver reduces them to 8 bit to make them fit into hardware registers. v3: - fix tags (Javier) Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/20250520094203.30545-3-tzimmermann@suse.de
2025-05-26drm: Add helpers for programming hardware gamma LUTsThomas Zimmermann1-0/+206
Provide helpers that program hardware gamma LUTs. Tha gamma ramp is either provided by the driver or generated by the helper. The DRM driver exports the GAMMA_LUT property with a fixed number of entries per color component, such as 256 on 8-bit-wide components. The entries describe the gamma ramp of each individual component. The new helper drm_crtc_load_gamma_888() loads such gamma ramp to hardware. The hardware uses each displayed pixel's individial components as indices into the hardware gamma table. For color modes with less than 8 bits per color component, the helpers drm_crtc_load_gamma_565_from() and drm_crtc_load_gamma_555_from_888() interpolate the provided gamma ramp to reduce it to the correct number of entries; 5/6/5 for RGB565-like formats and 5/5/5 for XRGB1555-like formats. If no gamma ramp has been provided, drivers can use the new helper drm_crtc_fill_gamma_888() to load a default gamma ramp with 256 entries per color component. For color modes with less bits, the new helpers drm_crtc_fill_gamma_565() and drm_crtc_fill_gamma_555() are available. The default gamma ramp uses a gamma factor of 1. For color modes with palette, drm_crtc_load_palette_8() load an 8-bit palette into the hardware. If no palette has been specified, drm_crtc_fill_palette_8() load a system-specific default palette. This is currently only a grey-scale palette with increasing luminance, but later patches can change this. For PCs, a VGA default palette could be used. v2: - drop comment on gamma factor of 2.2 (Michel, Pekka) - fix typos in commit description (Javier) Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Acked-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20250520094203.30545-2-tzimmermann@suse.de
2025-05-26drm/gem-framebuffer: log errors when gem size < afbc_sizeAndy Yan1-1/+4
Let the user know what went wrong in drm_gem_fb_afbc_init failure paths. Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250508084811.2472877-1-andyshrk@163.com
2025-05-26drm: drm_auth: Convert mutex usage to guard(mutex)André Almeida1-41/+23
Replace open-coded mutex handling with cleanup.h guard(mutex). This simplifies the code and removes the "goto unlock" pattern. Tested with igt tests core_auth and core_setmaster. Signed-off-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250509142627.639419-1-andrealmeid@igalia.com
2025-05-24drm: renesas: rz-du: Add support for RZ/V2H(P) SoCLad Prabhakar1-0/+11
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250512182330.238259-3-prabhakar.mahadev-lad.rj@bp.renesas.com
2025-05-24drm: renesas: rz-du: Add atomic_pre_enableChris Brandt1-2/+10
When drm_panel.prepare_prev_first is set to true in a panel driver, the panel expects the MIPI DSI hardware to be already configured before the panel's prepare function is called because it might need to send DCS commands. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Tested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250521210335.3149065-1-chris.brandt@renesas.com
2025-05-24drm: panel: Add support for Renesas R69328 based MIPI DSI panelMaxim Schwalm3-0/+295
Driver adds support for panels with Renesas R69328 IC Currently supported compatible is: - jdi,dx12d100vm0eaa Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250506092718.106088-5-clamor95@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-24drm: panel: Add support for Renesas R61307 based MIPI DSI panelSvyatoslav Ryhel3-0/+339
R61307 is liquid crystal driver for high-definition amorphous silicon (a-Si) panels and is ideal for tablets and smartphones. Supported compatibles are: - hit,tx13d100vm0eaa - koe,tx13d100vm0eaa Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250506092718.106088-3-clamor95@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-24drm/nouveau/tegra: Fix error pointer vs NULL return in ↵Dan Carpenter1-1/+1
nvkm_device_tegra_resource_addr() The nvkm_device_tegra_resource() function returns a mix of error pointers and NULL. The callers only expect it to return NULL on error. Change it to only return NULL. Fixes: 76b8f81a5b92 ("drm/nouveau: improve handling of 64-bit BARs") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://lore.kernel.org/dri-devel/334404bdf60765cb5a8e855a74c688bc537531ee.camel@nvidia.com/T/#t
2025-05-24Merge tag 'drm-xe-next-fixes-2025-05-23' of ↵Dave Airlie2-4/+16
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next Driver Changes: - Fix a SLPC debugfs NULL pointer dereference (Aradhya) - Fix an arbitrary value sysfs read return (Aradhya) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Link: https://lore.kernel.org/r/aDAxCgfm7HJbrchD@fedora
2025-05-24drm/panel: nt37801: Fix IS_ERR() vs NULL check in probe()Dan Carpenter1-2/+2
The devm_drm_panel_alloc() function returns error pointers, it doesn't return NULL. Update the check to match. Fixes: 4fca6849864d ("drm/panel: Add Novatek NT37801 panel driver") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Link: https://lore.kernel.org/r/aDCdn9r_ZAUTRpWn@stanley.mountain Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-24Merge tag 'drm-xe-fixes-2025-05-23' of ↵Dave Airlie2-10/+11
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Make sure to check all forcewakes when dumping mocs - Fix wrong use of read64 on 32b register - Synchronize Panther Lake PCI IDs Signed-off-by: Dave Airlie <airlied@redhat.com> From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/uixp5cq7emz32lmwwvq4vbujppugfozhyj3cm2aqzx4lcg7ivn@m2khvf4kvz5p
2025-05-24Merge tag 'amd-drm-fixes-6.15-2025-05-22' of ↵Dave Airlie1-5/+0
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.15-2025-05-22: amdgpu: - Hibernate fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250522183941.9606-1-alexander.deucher@amd.com
2025-05-24Merge tag 'drm-misc-fixes-2025-05-22' of ↵Dave Airlie1-0/+1
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: edid: - fix HDR metadata reset Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250522113902.GA7000@localhost.localdomain
2025-05-23drm/panel: nt37801: select CONFIG_DRM_DISPLAY_DSC_HELPERArnd Bergmann1-0/+2
The newly added driver uses the DSC helper module, but does not select its Kconfig symbol, so configurations are possible that cause a link failure: ERROR: modpost: "drm_dsc_pps_payload_pack" [drivers/gpu/drm/panel/panel-novatek-nt37801.ko] undefined! Fixes: 4fca6849864d ("drm/panel: Add Novatek NT37801 panel driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250523121127.2269693-1-arnd@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-23drm: convert many bridge drivers from devm_kzalloc() to ↵Luca Ceresoli49-198/+201
devm_drm_bridge_alloc() API devm_drm_bridge_alloc() is the new API to be used for allocating (and partially initializing) a private driver struct embedding a struct drm_bridge. For many drivers having a simple code flow in the probe function, this commit does a mass conversion automatically with the following semantic patch. The changes have been reviewed manually for correctness as well as to find any false positives. The patch has been applied with the explicit exclusion of bridge/panel.c, handled by a separate patch. After applying the semantic patch, manually fixed these issues: - 4 drivers need ERR_CAST() instead of PTR_ERR() as the function calling devm_drm_bridge_alloc() returns a pointer - re-added empty lines and comments that the script had removed but that should stay @@ type T; identifier C; identifier BR; expression DEV; expression FUNCS; @@ -T *C; +T *C; ... ( -C = devm_kzalloc(DEV, ...); -if (!C) - return -ENOMEM; +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS); +if (IS_ERR(C)) + return PTR_ERR(C); | -C = devm_kzalloc(DEV, ...); -if (!C) - return ERR_PTR(-ENOMEM); +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS); +if (IS_ERR(C)) + return PTR_ERR(C); ) ... -C->BR.funcs = FUNCS; Reviewed-by: Manikandan Muralidharan <manikandan.m@microchip.com> # microchip-lvds.c Reviewed-by: Douglas Anderson <dianders@chromium.org> # parade-ps8640 Tested-by: Douglas Anderson <dianders@chromium.org> # parade-ps8640 Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20250509-drm-bridge-convert-to-alloc-api-v3-2-b8bc1f16d7aa@bootlin.com [Luca: fixed trivial patch conflict in adv7511_drv.c while applying] Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2025-05-23drm/i915/display: Use str_true_false() helperYumeng Fang1-2/+3
Remove hard-coded strings by using the str_true_false() helper. Signed-off-by: Yumeng Fang <fang.yumeng@zte.com.cn> Signed-off-by: Yunjian Long <long.yunjian@zte.com.cn> Link: https://lore.kernel.org/r/20250523141422844GEA-yzba-OvN0lZirDsS-@zte.com.cn Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-23drm/xe: Default auto_link_downgrade status to falseAradhya Bhatia1-1/+2
xe_pcode_read() can return back successfully without updating the variable 'val'. This can cause an arbitrary value to show up in the sysfs file. Allow the auto_link_downgrade_status to default to 0 to avoid any arbitrary value from coming up. Fixes: 0e414bf7ad01 ("drm/xe: Expose PCIe link downgrade attributes") Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com> Link: https://lore.kernel.org/r/20250516124355.4872-1-aradhya.bhatia@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit a7f87deac2295d11865048bcb9c2de369b52ed93) Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
2025-05-23drm/xe/guc: Make creation of SLPC debugfs files conditionalAradhya Bhatia1-3/+14
Platforms that do not support SLPC are exempted from the GuC PC support. The GuC PC does not get initialized, and neither do its BOs get created. This causes a problem because the GuC PC debugfs file is still being created. Whenever the file is attempted to read, it causes a NULL pointer dereference on the supposed BO of the GuC PC. So, make the creation of SLPC debugfs files conditional to when SLPC features are supported. Fixes: aaab5404b16f ("drm/xe: Introduce GuC PC debugfs") Suggested-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com> Link: https://lore.kernel.org/r/20250516141902.5614-1-aradhya.bhatia@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit 17486cf3df5320752cc67ee8bcb2379d1b9de76c) Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
2025-05-23drm/xe: Use xe_mmio_read32() to read mtcfg registerShuicheng Lin1-5/+5
The mtcfg register is a 32-bit register and should therefore be accessed using xe_mmio_read32(). Other 3 changes per codestyle suggestion: " xe_mmio.c:83: CHECK: Alignment should match open parenthesis xe_mmio.c:131: CHECK: Comparison to NULL could be written "!xe->mmio.regs" xe_mmio.c:315: CHECK: line length of 103 exceeds 100 columns " Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://lore.kernel.org/r/20250513153010.3464767-1-shuicheng.lin@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit d2662cf8f44a68deb6c76ad9f1d9f29dbf7ba601) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-05-23drm/xe/mocs: Check if all domains awakeTejas Upadhyay1-5/+6
Check if all domains are awake specially for LNCF regs Fixes: 298661cd9cea ("drm/xe: Fix MOCS debugfs LNCF readout") Improvements-suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Badal Nilawar <badal.nilawar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250506142300.1865783-1-tejas.upadhyay@intel.com Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> (cherry picked from commit a383cf218ef8bb35d4c03958bd956573b65cf778) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-05-23drm/i915: track_pfn() -> "pfnmap tracking"David Hildenbrand1-2/+2
track_pfn() does not exist, let's simply refer to it as "pfnmap tracking". Link: https://lkml.kernel.org/r/20250512123424.637989-11-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Acked-by: Ingo Molnar <mingo@kernel.org> [x86 bits] Reviewed-by: Liam R. Howlett <Liam.Howlett@oracle.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Betkov <bp@alien8.de> Cc: Dave Airlie <airlied@gmail.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Jann Horn <jannh@google.com> Cc: Jonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: "Masami Hiramatsu (Google)" <mhiramat@kernel.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Peter Xu <peterx@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Thomas Gleinxer <tglx@linutronix.de> Cc: Tvrtko Ursulin <tursulin@ursulin.net> Cc: Vlastimil Babka <vbabka@suse.cz> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2025-05-22Revert "drm/amd: Keep display off while going into S4"Mario Limonciello1-5/+0
commit 68bfdc8dc0a1a ("drm/amd: Keep display off while going into S4") attempted to keep displays off during the S4 sequence by not resuming display IP. This however leads to hangs because DRM clients such as the console can try to access registers and cause a hang. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4155 Fixes: 68bfdc8dc0a1a ("drm/amd: Keep display off while going into S4") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250522141328.115095-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e485502c37b097b0bd773baa7e2741bf7bd2909a) Cc: stable@vger.kernel.org
2025-05-22drm/panel: abstract of_panel_find()Jani Nikula1-7/+16
Add a helper to wrap OF-specific calls in drm_panel_add_follower() in preparation for adding an ACPI equivalent in the future. No functional changes. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250522100036.2529624-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-22Revert "drm/amd: Keep display off while going into S4"Mario Limonciello1-5/+0
commit 68bfdc8dc0a1a ("drm/amd: Keep display off while going into S4") attempted to keep displays off during the S4 sequence by not resuming display IP. This however leads to hangs because DRM clients such as the console can try to access registers and cause a hang. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4155 Fixes: 68bfdc8dc0a1a ("drm/amd: Keep display off while going into S4") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250522141328.115095-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amd/pm: Fetch partition metrics on SMUv13.0.12Lijo Lazar3-0/+68
Add support to fetch compute partition related metrics in SMUv13.0.12 SOCs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22Revert "drm/amd/display: [FW Promotion] Release 0.1.11.0"Aurabindo Pillai1-32/+2
This reverts commit 81fc9ca25f02c53c055b842a40f2a915bd0bd5e0 since it introduces incompatbility with older firmware Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: seq64 memory unmap uses uninterruptible lockPhilip Yang1-1/+1
To unmap and free seq64 memory when drm node close to free vm, if there is signal accepted, then taking vm lock failed and leaking seq64 va mapping, and then dmesg has error log "still active bo inside vm". Change to use uninterruptible lock fix the mapping leaking and no dmesg error log. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: update ras support checkMangesh Gadre1-1/+2
update ras support check for vcn 5.0.1 Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: Enable RAS for jpeg 5.0.1Mangesh Gadre2-0/+192
Enable jpeg ras posion processing and aca error logging Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: Add jpeg poison status regMangesh Gadre2-0/+14
added registers to enable jpeg ras Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: Enable RAS for vcn 5.0.1Mangesh Gadre2-1/+171
Enable vcn ras posion processing and aca error logging Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amd/display: Add a new dcdebugmask to allow skip detection LTWayne Lin2-0/+8
Under specific embedded scenarios, we might still use DP interface rather than eDP interface. Under such case, detection link training is unnecessary. Add a new dcdebugmask value that can be used to skip the detection LT Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Link: https://lore.kernel.org/amd-gfx/20250521063934.2111323-1-Wayne.Lin@amd.com/ Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-12 19:28:22 +0300