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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2016-06-01drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)Kumar, Mahesh1-4/+9
2016-06-01drm/i915/skl+: calculate plane pixel rate (v4)Kumar, Mahesh1-3/+70
2016-06-01drm/i915/skl+: calculate ddb minimum allocation (v6)Kumar, Mahesh1-5/+65
2016-06-01drm/i915: Don't try to calculate relative data rates during hw readoutMatt Roper1-18/+0
2016-06-01drm/i915: Only ignore eDP ports that are connectedChris Wilson3-18/+17
2016-06-01drm/i915: Update GEN6_PMINTRMSK setup with GuC enabledSagar Arun Kamble5-14/+30
2016-05-30drm/i915: kill STANDARD/CURSOR plane screamsVille Syrjälä1-22/+15
2016-05-30drm/i915: Give encoders useful namesVille Syrjälä10-11/+25
2016-05-30drm/i915: Give meaningful names to all the planesVille Syrjälä2-9/+32
2016-05-30drm/i915: Don't leak primary/cursor planes on crtc init failureVille Syrjälä1-6/+6
2016-05-30drm/i915: Set crtc->name to "pipe A", "pipe B", etc.Ville Syrjälä1-1/+2
2016-05-30drm/i915: Use plane->name in debug printsVille Syrjälä1-16/+22
2016-05-30drm/i915: Use crtc->name in debug messagesVille Syrjälä3-24/+28
2016-05-27drm/i915: Reject modeset if the dotclock is too highVille Syrjälä1-9/+9
2016-05-26drm/i915: Fix NULL pointer deference when out of PLLs in IVBAnder Conselvan de Oliveira1-0/+3
2016-05-26drm/i915/ilk: Don't disable SSC source if it's in useLyude1-13/+36
2016-05-25drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resumeImre Deak1-2/+49
2016-05-25drm/i915/gen9: Assume CDCLK PLL is off if it's not lockedImre Deak1-23/+16
2016-05-25drm/i915: Revert async unpin and nonblocking atomic commitDaniel Vetter11-625/+1283
2016-05-24drm/i915/debugfs: Show context objects in i915_gem_objectsChris Wilson1-1/+37
2016-05-24drm/i915: Rearrange i915_gem_contextChris Wilson1-7/+9
2016-05-24drm/i915: Merge legacy+execlists context structsChris Wilson5-95/+56
2016-05-24drm/i915: Put the kernel_context in drm_i915_private next to its friendsChris Wilson2-4/+4
2016-05-24drm/i915: Show i915_gem_context owner in debugfsChris Wilson2-3/+18
2016-05-24drm/i915: Move pinning of dev_priv->kernel_context into its creatorChris Wilson1-29/+24
2016-05-24drm/i915: Name the inner most per-engine intel_context structChris Wilson3-56/+51
2016-05-24drm/i915: Rename and inline i915_gem_context_get()Chris Wilson3-21/+20
2016-05-24drm/i915: Apply lockdep annotations to i915_gem_context.cChris Wilson2-3/+16
2016-05-24drm/i915: Rename struct intel_contextChris Wilson12-82/+84
2016-05-24drm/i915/guc: Disable automatic GuC firmware loadingTvrtko Ursulin1-2/+2
2016-05-23drm/i915: Assert the dbuf is enabled when disabling DC5/6Ville Syrjälä1-0/+11
2016-05-23drm/i915: Set BXT cdclk to minimum initiallyVille Syrjälä1-7/+2
2016-05-23drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk checkVille Syrjälä3-20/+4
2016-05-23drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE P...Ville Syrjälä1-65/+63
2016-05-23drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vc...Ville Syrjälä1-14/+19
2016-05-23drm/i915: Update cached cdclk state from broxton_init_cdclk()Ville Syrjälä1-6/+3
2016-05-23drm/i915: Store BXT DE PLL vco and ref clocks in dev_privVille Syrjälä1-1/+26
2016-05-23drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()Ville Syrjälä1-14/+27
2016-05-23drm/i915: Store cdclk PLL reference clock under dev_privVille Syrjälä2-7/+9
2016-05-23drm/i915: Rename skl_vco_freq to cdclk_pll.vcoVille Syrjälä3-29/+31
2016-05-23drm/i915: Make 308 and 671 MHz cdclks more accurate on SKLVille Syrjälä1-9/+9
2016-05-23drm/i915: Move SKL+ DBUF enable/disable to display core init/uninitVille Syrjälä2-52/+38
2016-05-23drm/i915: Unify SKL cdclk init pathsVille Syrjälä4-23/+34
2016-05-23drm/i915: Beef up skl_sanitize_cdclk() a bitVille Syrjälä1-5/+13
2016-05-23drm/i915: Keep track of preferred cdclk vco frequency on SKLVille Syrjälä4-8/+47
2016-05-23drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKLVille Syrjälä1-25/+29
2016-05-23drm/i915: Report the current DPLL0 vco on SKL/KBLVille Syrjälä1-2/+7
2016-05-23drm/i915: Actually read out DPLL0 vco on skl from hardwareVille Syrjälä2-42/+37
2016-05-23drm/i915: Extract skl_calc_cdclk()Ville Syrjälä1-33/+30
2016-05-23drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()Ville Syrjälä2-4/+21
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