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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2015-09-02drm/i915: Add port A HPD support for ILK/SNBVille Syrjälä1-3/+56
2015-09-02drm/i915: Introduce spt_irq_handler()Ville Syrjälä1-40/+84
2015-09-02drm/i915: Move {pin, long}_mask initialization to caller from intel_get_hpd_p...Ville Syrjälä1-8/+11
2015-09-02drm/i915: Rename BXT PORTA HPD definesVille Syrjälä2-6/+6
2015-09-02drm/i915: Add HAS_PCH_LPT_LP() macroVille Syrjälä3-10/+8
2015-09-02drm/i915: Factor out ilk_update_display_irq()Ville Syrjälä1-15/+26
2015-09-02drm/i915: Extract intel_hpd_enabled_irqs()Ville Syrjälä1-22/+21
2015-09-02drm/i915: Clean up various HPD definesVille Syrjälä1-36/+38
2015-09-02drm/i915: Update comments around base bppDaniel Vetter1-5/+1
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter360-14580/+45394
2015-09-02drm/i915: Also record time difference if vblank evasion fails, v2.Maarten Lankhorst2-2/+7
2015-09-02drm/i915: Remove start frame argument to pipe_update_begin/end.Maarten Lankhorst3-15/+14
2015-09-02drm/i915: guest i915 notification for Intel GVT-gZhiyuan Lv1-0/+41
2015-09-02drm/i915: Update PV INFO page definition for Intel GVT-gZhiyuan Lv1-2/+32
2015-09-02drm/i915: Always enable execlists on BDW for vgpuZhiyuan Lv2-0/+13
2015-09-02drm/i915: preallocate pdps for 32 bit vgpuZhiyuan Lv2-1/+35
2015-09-02drm/i915: add yesno utility functionJani Nikula3-10/+5
2015-09-02drm/i915: move intel_hrawclk() to intel_display.cJani Nikula3-34/+34
2015-09-02drm/i915: Notify GuC rc6 stateAlex Dai1-0/+15
2015-09-02drm/i915/guc: Support GuC version 4.3Alex Dai2-14/+14
2015-09-02drm/i915: Fix module initialisation, v2.Maarten Lankhorst3-18/+7
2015-09-01drm/i915: Factor out intel_crtc_has_encoders()Ville Syrjälä1-9/+13
2015-09-01drm/i915: Fix clock readout when pipes are enabled w/o portsVille Syrjälä1-0/+8
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2-17/+111
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2-0/+62
2015-09-01drm/i915: Clean up CHV lane soft reset programmingVille Syrjälä2-82/+100
2015-09-01i915: Set ddi_pll_sel in DP MST pathAnder Conselvan de Oliveira3-1/+7
2015-09-01drm/i915: Bump command parser version number.Francisco Jerez1-1/+2
2015-09-01drm/i915/dp: use the drm dp helper for determining sink tps3 supportJani Nikula1-2/+1
2015-09-01drm/i915: Don't use link_bw for PLL setupVille Syrjälä2-29/+26
2015-09-01drm/i915: Preserve SSC earlierLukas Wunner1-11/+18
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang4-1/+7
2015-08-31drm/i915: eDP can be present on DDI-ERodrigo Vivi2-9/+5
2015-08-31drm/i915/skl: Enable DDI-ERodrigo Vivi3-7/+18
2015-08-31drm/i915: Enable HDMI on DDI-EXiong Zhang3-4/+47
2015-08-31drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6Imre Deak1-6/+9
2015-08-31drm/i915: Check DP link status on long hpd tooVille Syrjälä1-6/+5
2015-08-28drm/i915: set CDCLK if DPLL0 enabled during resuming from S3Gary Wang1-8/+5
2015-08-28drm/i915: Update DRIVER_DATE to 20150828Daniel Vetter1-1/+1
2015-08-26Partially revert "drm/i915: Use full atomic modeset."Maarten Lankhorst3-1/+7
2015-08-26drm/i915: gen 9 can check for unclaimed registers tooPaulo Zanoni2-0/+8
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä2-0/+10
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä2-1/+6
2015-08-26drm/i915: Force common lane on for the PPS kick on CHVVille Syrjälä1-3/+13
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä4-0/+78
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä5-59/+221
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä1-21/+24
2015-08-26drm/i915: Make some string arrays constVille Syrjälä1-2/+2
2015-08-26drm/i915: Use ARRAY_SIZE() instead of hand rolling itVille Syrjälä3-4/+3
2015-08-26drm/i915: Fix some gcc warningsVille Syrjälä1-2/+2
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