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This will help debug issues with TLB invalidation fences.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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This gets tricky as we can't do the TLB invalidation until the unbind
operation is done on the hardware and we can't signal the unbind as
complete until the TLB invalidation is done. To work around this we
create an unbind fence which does a TLB invalidation after unbind is
done on the hardware, signals on TLB invalidation completion, and this
fence is installed in the BO dma-resv slot and installed in out-syncs
for the unbind operation.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Suggested-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com
Suggested-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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On DG2 when running the xe_vm IGT, the kernel generates loads of CAT
errors and GT resets (sometimes at least). On small-bar systems seems
to trigger a lot more easily (maybe due to difference in allocation
strategy). Appears to be related to scratch, since we seem to use the
64K TLB hint on scratch entries, even though the scratch page is a 4K
vram page. Bumping the scratch page size and physical alignment seems
to fix it. Or at least we no longer hit:
[ 148.872683] xe 0000:03:00.0: [drm] Engine memory cat error: guc_id=0
[ 148.872701] xe 0000:03:00.0: [drm] Engine memory cat error: guc_id=0
[ 148.875108] WARNING: CPU: 0 PID: 953 at drivers/gpu/drm/xe/xe_guc_submit.c:797
However to keep things simple, so we don't have to deal with 64K TLB
hints, just move the scratch page into system memory on platforms that
require 64K VRAM pages.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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We need to ensure we don't leak the contents to userspace.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Fix the below splat:
[ 142.510525] [IGT] xe_exec_basic: starting subtest once-userptr
[ 142.511339] BUG: kernel NULL pointer dereference, address: 0000000000000228
[ 142.518311] #PF: supervisor read access in kernel mode
[ 142.523458] #PF: error_code(0x0000) - not-present page
[ 142.528604] PGD 0 P4D 0
[ 142.531153] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ 142.535518] CPU: 4 PID: 1199 Comm: kworker/u16:8 Not tainted 6.1.0-rc1-xe+ #1
[ 142.542656] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.3243.A01.2006102133 06/10/2020
[ 142.556033] Workqueue: events_unbound async_op_work_func [xe]
[ 142.561810] RIP: 0010:xe_bo_is_stolen+0x0/0x20 [xe]
[ 142.566709] Code: 20 c8 75 05 83 fa 07 74 05 c3 cc cc cc cc 48 8b 87 08 02 00 00 0f b6 80 2c ff ff ff c3 cc cc cc cc 66 0f 1f 84 00 00 00 00 00 <48> 8b 87 28 02 00 00 83 78 10 07 0f 94 c0 c3 cc cc cc cc 66 66 2e
[ 142.585447] RSP: 0018:ffffc900019eb888 EFLAGS: 00010246
[ 142.590678] RAX: 0000000000000002 RBX: 0000000000000000 RCX: ffff88813f6a2108
[ 142.597821] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
[ 142.604962] RBP: ffffc900019ebbc0 R08: 0000000000000001 R09: 0000000000000000
[ 142.612101] R10: 0000000000000001 R11: 0000000000000001 R12: ffff88814107d600
[ 142.619242] R13: ffffc900019eba20 R14: ffff888140442000 R15: 0000000000000000
[ 142.626378] FS: 0000000000000000(0000) GS:ffff88849fa00000(0000) knlGS:0000000000000000
[ 142.634468] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 142.640219] CR2: 0000000000000228 CR3: 000000010a4c0006 CR4: 0000000000770ee0
[ 142.647361] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 142.654505] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 142.661639] PKRU: 55555554
[ 142.664367] Call Trace:
[ 142.666830] <TASK>
[ 142.668947] __xe_pt_bind_vma+0x1a1/0xa50 [xe]
[ 142.673417] ? unwind_next_frame+0x187/0x770
[ 142.677699] ? __thaw_task+0xc0/0xc0
[ 142.681293] ? __lock_acquire+0x5e4/0x26e0
[ 142.685409] ? lockdep_hardirqs_on+0xbf/0x140
[ 142.689779] ? lock_acquire+0xd2/0x310
[ 142.693548] ? mark_held_locks+0x49/0x80
[ 142.697485] ? xe_vm_bind_vma+0xf1/0x3d0 [xe]
[ 142.701866] xe_vm_bind_vma+0xf1/0x3d0 [xe]
[ 142.706082] xe_vm_bind+0x76/0x140 [xe]
[ 142.709944] vm_bind_ioctl+0x26f/0xb40 [xe]
[ 142.714161] ? async_op_work_func+0x20c/0x450 [xe]
[ 142.718974] async_op_work_func+0x20c/0x450 [xe]
[ 142.723620] process_one_work+0x263/0x580
[ 142.727645] ? process_one_work+0x580/0x580
[ 142.731839] worker_thread+0x4d/0x3b0
[ 142.735518] ? process_one_work+0x580/0x580
[ 142.739714] kthread+0xeb/0x120
[ 142.742872] ? kthread_complete_and_exit+0x20/0x20
[ 142.747671] ret_from_fork+0x1f/0x30
[ 142.751264] </TASK>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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This adds support for stolen memory, with the same allocator as
vram_mgr. This allows us to skip a whole lot of copy-paste,
by re-using parts of xe_ttm_vram_mgr.
The stolen memory may be bound using VM_BIND, so it performs like any
other memory region.
We should be able to map a stolen BO directly using the physical memory
location instead of through GGTT even on old platforms, but I don't know
what the effects are on coherency.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Xe, is a new driver for Intel GPUs that supports both integrated and
discrete platforms starting with Tiger Lake (first Intel Xe Architecture).
The code is at a stage where it is already functional and has experimental
support for multiple platforms starting from Tiger Lake, with initial
support implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan
drivers), as well as in NEO (for OpenCL and Level0).
The new Xe driver leverages a lot from i915.
As for display, the intent is to share the display code with the i915
driver so that there is maximum reuse there. But it is not added
in this patch.
This initial work is a collaboration of many people and unfortunately
the big squashed patch won't fully honor the proper credits. But let's
get some git quick stats so we can at least try to preserve some of the
credits:
Co-developed-by: Matthew Brost <matthew.brost@intel.com>
Co-developed-by: Matthew Auld <matthew.auld@intel.com>
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Co-developed-by: Francois Dugast <francois.dugast@intel.com>
Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Co-developed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Co-developed-by: Philippe Lecluse <philippe.lecluse@intel.com>
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Co-developed-by: Jani Nikula <jani.nikula@intel.com>
Co-developed-by: José Roberto de Souza <jose.souza@intel.com>
Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Co-developed-by: Dave Airlie <airlied@redhat.com>
Co-developed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Co-developed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
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