summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/tegra
AgeCommit message (Expand)AuthorFilesLines
2015-02-19drm/tegra: dc: Move more code into ->init()Thierry Reding1-38/+36
2015-02-19drm/tegra: dc: Wire up CRTC parent of atomic stateThierry Reding1-1/+3
2015-02-19drm/tegra: dc: Reset state's active_changed fieldThierry Reding1-0/+1
2015-02-19drm/tegra: hdmi: Explicitly set clock rateThierry Reding1-0/+8
2015-01-27drm/tegra: Use correct relocation target offsetsDavid Ung1-1/+1
2015-01-27drm/tegra: Add minimal power managementThierry Reding1-0/+25
2015-01-27drm/tegra: dc: Unify enabling the display controllerThierry Reding5-52/+16
2015-01-27drm/tegra: Track tiling and format in plane stateThierry Reding2-30/+101
2015-01-27drm/tegra: Track active planes in CRTC stateThierry Reding1-28/+44
2015-01-27drm/tegra: Remove unused ->mode_fixup() callbacksThierry Reding4-179/+0
2015-01-27drm/tegra: Atomic conversion, phase 3, step 3Thierry Reding3-119/+100
2015-01-27drm/tegra: Atomic conversion, phase 3, step 2Thierry Reding1-1/+1
2015-01-27drm/tegra: dc: Use atomic clock state in modesetThierry Reding1-0/+37
2015-01-27drm/tegra: sor: Implement ->atomic_check()Thierry Reding1-0/+22
2015-01-27drm/tegra: hdmi: Implement ->atomic_check()Thierry Reding1-0/+22
2015-01-27drm/tegra: dsi: Implement ->atomic_check()Thierry Reding1-73/+196
2015-01-27drm/tegra: rgb: Implement ->atomic_check()Thierry Reding1-0/+42
2015-01-27drm/tegra: dc: Store clock setup in atomic stateThierry Reding2-3/+72
2015-01-27drm/tegra: Atomic conversion, phase 3, step 1Thierry Reding2-6/+10
2015-01-27drm/tegra: Atomic conversion, phase 2Thierry Reding6-0/+22
2015-01-27drm/tegra: Atomic conversion, phase 1Thierry Reding7-185/+223
2015-01-27drm/tegra: dc: Do not needlessly deassert resetThierry Reding1-4/+0
2015-01-27drm/tegra: Output cleanup functions cannot failThierry Reding6-32/+13
2015-01-27drm/tegra: Remove remnants of the output midlayerThierry Reding7-212/+32
2015-01-27drm/tegra: debugfs cleanup cannot failThierry Reding3-27/+9
2015-01-27drm/tegra: sor: DemidlayerThierry Reding3-368/+410
2015-01-27drm/tegra: dsi: DemidlayerThierry Reding3-169/+195
2015-01-27drm/tegra: hdmi: DemidlayerThierry Reding3-139/+147
2015-01-27drm/tegra: rgb: DemidlayerThierry Reding4-112/+161
2015-01-27drm/tegra: Add tegra_dc_setup_clock() helperThierry Reding2-0/+22
2015-01-27drm/tegra: output: Make ->setup_clock() optionalThierry Reding2-11/+9
2015-01-27drm/tegra: Convert output midlayer to helpersThierry Reding2-12/+21
2015-01-27drm/tegra: dc: No longer disable planes at CRTC disableThierry Reding1-14/+0
2015-01-27drm/tegra: Move tegra_drm_mode_funcs to the coreThierry Reding3-21/+23
2015-01-27drm/tegra: dc: Wait for idle when disabledThierry Reding1-5/+65
2015-01-27drm/tegra: Stop CRTC at CRTC disable timeThierry Reding5-16/+6
2015-01-27drm/tegra: Use tegra_commit_dc() in output driversThierry Reding6-18/+11
2015-01-27drm/tegra: gem: oops in error handlingDan Carpenter1-3/+2
2015-01-27drm/tegra: dc: Fix bad irqsave/restore in tegra_dc_finish_page_flip()Dan Carpenter1-2/+2
2015-01-27drm/tegra: dsi: Adjust D-PHY timingDavid Ung1-6/+19
2015-01-27drm/tegra: dsi: Reset across ->exit()/->init()Thierry Reding1-13/+14
2015-01-27drm/tegra: dsi: Soft-reset controller on ->disableThierry Reding1-0/+25
2015-01-27drm/tegra: dsi: Registers are 32-bitThierry Reding1-7/+7
2015-01-27drm/tegra: hdmi: Registers are 32-bitThierry Reding1-18/+18
2015-01-27drm/tegra: dc: Return planar flag for non-YUV modesThierry Reding1-0/+3
2015-01-27drm/tegra: dc: Describe register copiesThierry Reding1-0/+12
2015-01-27drm/tegra: dc: Initialize border colorThierry Reding1-0/+8
2015-01-27drm/tegra: Check for NULL pointer instead of IS_ERR()Dan Carpenter1-2/+2
2015-01-27drm/tegra: plane: Use proper possible_crtcs maskThierry Reding1-1/+14
2015-01-27drm/tegra: Remove redundant zeroing out of memoryThierry Reding2-18/+0
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-25 18:44:55 +0300