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path: root/drivers/gpu/drm/rockchip
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2017-04-07drm/rockchip: Shutdown all crtcs when unbinding drmJeffy Chen1-0/+1
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-12-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: Reorder drm bind/unbind sequenceJeffy Chen1-23/+26
Current drm bind/unbind sequence would cause some memory issues. For example we should not cleanup iommu before cleanup mode config. Reorder bind/unbind sequence, follow exynos drm. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> [seanpaul fixed spelling typo in commit subject] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-11-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: analogix_dp: Disable clock when unbindingJeffy Chen1-1/+2
The clock is enabled when binding cdn dp. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-10-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: vop: Unprepare clocks when unbindingJeffy Chen1-0/+4
The clocks are prepared when binding vop. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-9-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: vop: Enable pm domain before vop_initialJeffy Chen1-8/+21
We're trying to access vop registers here, so need to make sure the pm domain is on. Normally it should be enabled by the bootloader, but there's no guarantee of it. And if we wanna do unbind/bind, it would also cause the device to hang. And this patch also does these: 1/ move vop_initial to the end of vop_bind for eaiser error handling. 2/ correct the err_put_pm_runtime of vop_enable. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-8-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: cdn-dp: Don't unregister audio dev when unbindingJeffy Chen1-3/+3
After snd_soc_unregister_codec, the dai link would remain bound to the invalid codec. That would cause crashes after unbind dp driver. Let's unregister audio codec when removing dp driver to prevent that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-7-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm/rockchip: cdn-dp: Don't try to release firmware when not loadedJeffy Chen1-1/+3
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491481885-13775-6-git-send-email-jeffy.chen@rock-chips.com
2017-04-07drm: convert drivers to use drm_of_find_panel_or_bridgeRob Herring1-22/+4
Similar to the previous commit, convert drivers open coding OF graph parsing to use drm_of_find_panel_or_bridge instead. This changes some error messages to debug messages (in the graph core). Graph connections are often "no connects" depending on the particular board, so we want to avoid spurious messages. Plus the kernel is not a DT validator. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Archit Taneja <architt@codeaurora.org> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [seanpaul dropped rockchip changes since they're now obsolete] Signed-off-by: Sean Paul <seanpaul@chromium.org>
2017-03-24drm/rockchip/dsi: correct the grf_switch_reg nameChris Zhong1-2/+2
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1490147691-4489-5-git-send-email-zyw@rock-chips.com
2017-03-24drm/rockchip/dsi: enable the grf clk before writing grf registersChris Zhong1-1/+25
For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1490147691-4489-4-git-send-email-zyw@rock-chips.com
2017-03-24drm/rockchip/dsi: check phy_cfg_clk only for RK3399Chris Zhong1-6/+8
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1490147691-4489-2-git-send-email-zyw@rock-chips.com
2017-03-24drm/rockchip: Refactor the component match logic.Jeffy Chen10-108/+118
Currently we are adding all components from the dts, if one of their drivers been disabled, we would not be able to bring up others. Refactor component match logic, follow exynos drm. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Mark Yao <mark.yao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1490152880-21855-1-git-send-email-jeffy.chen@rock-chips.com
2017-03-14Merge tag 'doc-4.11-images' of git://git.lwn.net/linux into drm-misc-nextDaniel Vetter2-1/+4
Pointer for Markus's image conversion work. We need this so we can merge all the pretty drm graphs for 4.12. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2017-03-13drm/rockchip: cdn-dp: add more log for video configChris Zhong1-0/+4
In order to analyze some video config failed, add some useful printouts. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1488940077-22297-4-git-send-email-zyw@rock-chips.com
2017-03-13drm/rockchip: cdn-dp: Correct PHY register addressChris Zhong1-6/+5
Correct some DP register address for PHY Configuration according to latest datasheet. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1488940077-22297-3-git-send-email-zyw@rock-chips.com
2017-03-13drm/rockchip: cdn-dp: return error code when clk_get_rate failedChris Zhong3-4/+5
The clk_get_rate return 0 if something goes wrong, so it can never be less then zero, the ret should be set a error code, otherwise the cdn_dp_clk_enable will return 0 when it failed at clk_get_rate. In addition, clk_get_rate() returns an "unsigned long", so use "unsigned long" instead of "u32" is better. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1488940077-22297-2-git-send-email-zyw@rock-chips.com
2017-03-10drm: bridge: dw-hdmi: Remove device type from platform dataKieran Bingham1-1/+0
The device type isn't used anymore now that workarounds and PHY-specific operations are performed based on version information read at runtime. Remove it. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-9-laurent.pinchart+renesas@ideasonboard.com
2017-03-07drm/rockchip: Fix link error when CONFIG_DRM_ANALOGIX_DP undefinedSean Paul1-0/+10
Fixes the following link error when CONFIG_DRM_ANALOGIX_DP is not defined: ERROR: "analogix_dp_start_crc" [drivers/gpu/drm/rockchip/rockchipdrm.ko] undefined! ERROR: "analogix_dp_stop_crc" [drivers/gpu/drm/rockchip/rockchipdrm.ko] undefined! Fixes: 3190e58dafaf ("drm/rockchip: Implement CRC debugfs API") Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Mark Yao <mark.yao@rock-chips.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2017-03-06drm/rockchip: Implement CRC debugfs APITomeu Vizoso1-0/+41
Implement the .set_crc_source() callback and call the DP helpers accordingly to start and stop CRC capture. This is only done if this CRTC is currently using the eDP connector. v3: Remove superfluous check on rockchip_crtc_state->output_type v6: Remove superfluous variable Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170303133936.14964-5-tomeu.vizoso@collabora.com
2017-03-01drm/rockchip/dsi: add dw-mipi power domain supportChris Zhong1-0/+16
Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1487577744-2855-8-git-send-email-zyw@rock-chips.com
2017-03-01drm/rockchip/dsi: fix insufficient bandwidth of some panelChris Zhong1-2/+2
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-7-git-send-email-zyw@rock-chips.com
2017-03-01drm/rockchip/dsi: remove mode_valid functionChris Zhong1-39/+0
The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-5-git-send-email-zyw@rock-chips.com
2017-03-01drm/rockchip/dsi: dw-mipi: correct the coding styleChris Zhong1-15/+14
correct the coding style, according the checkpatch scripts Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-4-git-send-email-zyw@rock-chips.com
2017-03-01drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsiChris Zhong1-10/+62
The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-3-git-send-email-zyw@rock-chips.com
2017-03-01drm/rockchip: dw-mipi-dsi: add reset controlJohn Keeping1-0/+31
In order to fully reset the state of the MIPI controller we must assert this reset. This is slightly more complicated than it could be in order to maintain compatibility with device trees that do not specify the reset property. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-24-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: support non-burst modesJohn Keeping1-8/+13
Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-23-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: defer probe if panel is not loadedJohn Keeping1-3/+18
This ensures that the output resolution is known before fbcon loads. mipi_dsi_host_register() is moved above dw_mipi_dsi_register() to simplify error cleanup since the order of these operations does not matter. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-22-john@metanate.com
2017-03-01drm/rockchip: vop: test for P{H,V}SYNCJohn Keeping1-4/+4
When connected to the MIPI DSI output, we need to use N{H,V}SYNC for the internal connection but these flags are meaningless for DSI panels. Switch the test so that we do not set the P{H,V}SYNC bits unless the mode requires it. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> [seanpaul resolved conflict using macros instead of hardcoded values] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-21-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNCJohn Keeping1-2/+2
This matches other drivers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-20-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: use specific poll helperJohn Keeping1-5/+5
As the documentation for readx_poll_timeout says, we want to use the specialized macro for readl rather than using the generic version directly. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-19-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: improve PLL configurationJohn Keeping1-1/+12
The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-18-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: properly configure PHY timingJohn Keeping1-4/+31
These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-17-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: configure PHY before enablingJohn Keeping1-5/+6
The bias, bandgap and PLL should all be configured before we enable them. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-16-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: ensure PHY is resetJohn Keeping1-1/+4
Also don't power up the DSI host at this point since this is not necessary in order to configure the PHY and we do so later when selecting video or command mode. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-15-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: fix escape clock rateJohn Keeping1-1/+11
This clock rate is derived from the PHY PLL, so it should be calculated dynamically. This calculation is the same as that used by the vendor kernel and ensures that the escape clock runs at <20MHz as required by the MIPI specification. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-14-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: allow commands in panel_disableJohn Keeping1-10/+2
Panel drivers may want to sent commands during the disable function, for example MIPI_DCS_SET_DISPLAY_OFF before the video signal ends. In order to send commands we need to write to registers, so pclk must be enabled. While changing this, remove the unnecessary code after the panel unprepare call which seems to be a workaround for a specific panel and thus belongs in the panel driver. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-13-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: prepare panel after phy initJohn Keeping1-2/+4
Some panels need to be configured with commands sent over the MIPI link, which they will do in the prepare hook. Call this after the PHY has been initialized so that we are able to send commands to the panel. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-12-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: don't assume buffer is alignedJohn Keeping1-5/+7
By dereferencing the MIPI command buffer as a u32* we rely on it being correctly aligned on ARM, but this may not be the case. Copy it into a stack variable that will be correctly aligned. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-11-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: only request HS clock when requiredJohn Keeping1-2/+4
Requesting the HS clock from the PHY before we initialize it causes an invalid signal to be sent out since the input clock is not yet configured. The PHY databook suggests only asserting this signal when performing HS transfers, so let's do that. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-10-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: respect message flagsJohn Keeping1-1/+15
Instead of always sending commands in LP mode, respect the MIPI_DSI_MSG_USE_LPM flag to decide how to send each message. Also request acks if MIPI_DSI_MSG_REQ_ACK is set. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-9-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: include bad value in error messageJohn Keeping1-1/+2
As an aid to debugging. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-8-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_bufJohn Keeping1-2/+9
As a side-effect of this, encode the endianness explicitly rather than casting a u16. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-7-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: fix generic packet status checkJohn Keeping1-2/+3
We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits are set so we can't just check "val & mask" because that will be true if either bit is set. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-6-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: fix command header writesJohn Keeping1-4/+6
In a couple of places here we use "val" for the value that is about to be written to a register but then reuse the same variable for the value of a status register before we get around to writing it. Rename the value to be written to so that we write the value we intend to and not what we have just read from the status register. Signed-off-by: John Keeping <john@metanate.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-5-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: remove mode_set hookJohn Keeping1-12/+1
This is not needed since we can access the mode via the CRTC from the enable hook. Also remove the "mode" field that is no longer used. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-4-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: pass mode in where neededJohn Keeping1-19/+22
This shows that we only use the mode from the enable function and prepares us to remove the "mode" field and the mode_set hook in the next commit. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-3-john@metanate.com
2017-03-01drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPIJohn Keeping1-28/+21
With atomic modesetting the hardware will be powered off when the mode_set function is called. We should configure the hardware in the enable function, which is the atomic version of "commit" so let's use the enable hook rather than commit while we're at it. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-2-john@metanate.com
2017-02-28Merge tag 'drm-misc-next-fixes-2017-02-27' of ↵Dave Airlie2-1/+4
git://anongit.freedesktop.org/git/drm-misc into drm-next Misc fixes for the 4.11 merge window. - vmwgfx drm_control node compat patch - rockchip&zte fix - compat32 support for dma-buf ioctl (cc: stable ofc, since this is a massive fumble. oops) * tag 'drm-misc-next-fixes-2017-02-27' of git://anongit.freedesktop.org/git/drm-misc: dma-buf: add support for compat ioctl drm/vmwgfx: Work around drm removal of control nodes drm/rockchip: cdn-dp: Fix error handling drm/rockchip: add extcon dependency for DP drm: zte: fix static checker warning on variable 'fmt'
2017-02-26Merge airlied/drm-next into drm-misc-nextDaniel Vetter14-65/+3170
Backmerge the main pull request to sync up with all the newly landed drivers. Otherwise we'll have chaos even before 4.12 started in earnest. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2017-02-23drm/rockchip: cdn-dp: Fix error handlingChristophe JAILLET1-1/+3
It is likely that both 'clk_disable_unprepare()' should be called if 'pm_runtime_get_sync()' fails. Add a new label for that, because 'err_set_rate' is not meaningful in this case. Add a missing call to 'pm_runtime_put()'. Fixes: 1a0f7ed3abe2 ("drm/rockchip: cdn-dp: add cdn DP support for rk3399") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170220070815.23096-1-christophe.jaillet@wanadoo.fr
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