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path: root/drivers/gpu/drm/radeon/cikd.h
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2014-07-02drm/radeon/cik: fix typo in EOP packetAlex Deucher1-1/+1
Volatile bit was in the wrong location. This bit is not used at the moment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-05Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-nextDave Airlie1-0/+9
Merge drm-fixes into drm-next. Both i915 and radeon need this done for later patches. Conflicts: drivers/gpu/drm/drm_crtc_helper.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/i915_gem_execbuffer.c drivers/gpu/drm/i915/i915_gem_gtt.c
2014-06-02drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2Christian König1-0/+1
This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-05-01drm/radeon: use pflip irq on R600+ v2Christian König1-0/+9
Testing the update pending bit directly after issuing an update is nonsense cause depending on the pixel clock the CRTC needs a bit of time to execute the flip even when we are in the VBLANK period. This is just a non invasive patch to solve the problem at hand, a more complete and cleaner solution should follow in the next merge window. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: fix source IDs for CRTC2-6 Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2014-02-18drm/radeon: add support for vce 2.0 clock gatingAlex Deucher1-0/+10
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-18drm/radeon: fill in set_vce_clocks for CIK asicsAlex Deucher1-0/+6
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-18drm/radeon: initial VCE support v4Christian König1-0/+33
Only VCE 2.0 support so far. v2: squashing multiple patches into this one v3: add IRQ support for CIK, major cleanups, basic code documentation v4: remove HAINAN from chipset list Signed-off-by: Christian König <christian.koenig@amd.com>
2014-01-09drm/radeon: implement pci config reset for CIK (v3)Alex Deucher1-0/+11
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: fix rebase v3: hide behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update rb setup for hawaiiAlex Deucher1-1/+3
The formula needs to be adjusted since there are 4 RBs per SH rather than 2 as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update cik_tiling_mode_table_init() for hawaiiAlex Deucher1-0/+2
Hawaii uses a different tiling configuration. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: minor updates to cik.c for hawaiiAlex Deucher1-0/+1
Skip programming a register that was removed and adjust the mask of the VM client status. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update cik_gpu_init() for hawaiiAlex Deucher1-0/+1
This adds the hawaii asic specific configuration details. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: implement blit copy callback for CIKAlex Deucher1-0/+62
Uses the CP ring rather than the DMA ring. Useful for debugging and benchmarking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: Add support for programming the FMT blocksAlex Deucher1-0/+33
The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: update line buffer allocation for dce8Alex Deucher1-0/+4
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce8 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-31drm/radeon: restructure cg/pg on cik (v2)Alex Deucher1-0/+1
- use new cg/pg flags for finer grained clock and powergating control - restructure the cg/pg code so it can be called from other components such as dpm v2: fix build breakage from rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/dpm: add debugfs support for KB/KVAlex Deucher1-0/+4
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/dpm: add debugfs support for CIAlex Deucher1-0/+12
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher1-1/+258
This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/kms: add dpm support for KB/KVAlex Deucher1-0/+72
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher1-0/+8
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: add rlc helpers for DPMAlex Deucher1-0/+9
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher1-1/+94
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: restructure rlc setupAlex Deucher1-0/+1
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add support for ASPM on CIK asicsAlex Deucher1-1/+71
Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: add support for pcie gen1/2/3 switchingAlex Deucher1-0/+57
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14drm/radeon: add fault decode function for CIKAlex Deucher1-0/+16
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: Add support for compute queues (v4)Alex Deucher1-0/+62
On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: add UVD support for CIK (v3)Christian König1-0/+28
v2: agd5f: fix clock dividers setup for bonaire v3: agd5f: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add pcie_port indirect register accessorsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_xclk() callback for CIKAlex Deucher1-0/+7
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update CIK soft resetAlex Deucher1-0/+12
Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_gpu_clock_counter() callback for cikAlex Deucher1-1/+3
Used for GPU clock counter snapshots. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dce8: add support for display watermark setupAlex Deucher1-0/+11
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher1-0/+130
CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: log and handle VM page fault interruptsAlex Deucher1-0/+4
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add support for interrupts on CIK (v5)Alex Deucher1-0/+170
Todo: - handle interrupts for compute queues v2: add documentation v3: update to latest reset code v4: update to latest illegal CP handling v5: fix missing break in interrupt handler switch statement Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: Add support for RLC init on CIK (v4)Alex Deucher1-0/+47
RLC handles the interrupt controller and other tasks on the GPU. v2: add documentation v3: update programming sequence v4: additional setup Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)Alex Deucher1-3/+117
For gfx ring only. Compute is still todo. v2: add documentation v3: update to latest reset changes, integrate emit update patch. v4: fix count on wait_reg_mem for HDP flush v5: use old hdp flush method for fence v6: set valid bit for IB v7: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: Add CP init for CIK (v7)Alex Deucher1-0/+222
Sets up the GFX ring and loads ucode for GFX and Compute. Todo: - handle compute queue setup. v2: add documentation v3: integrate with latest reset changes v4: additional init fixes v5: scratch reg write back no longer supported on CIK v6: properly set CP_RB0_BASE_HI v7: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add support mc ucode loading on CIK (v2)Alex Deucher1-0/+16
Load the GDDR5 ucode and train the links. v2: update ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: stop page faults from hanging the system (v2)Alex Deucher1-0/+11
Redirect invalid memory accesses to the default page instead of locking up the memory controller. v2: rebase on top of 2 level PTs Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add support for MC/VM setup on CIK (v6)Alex Deucher1-0/+125
The vm callbacks are the same as the SI ones right now (same regs and bits). We could share the SI variants, and I may yet do that, but I figured I would add CIK specific ones for now in case we need to change anything. V2: add documentation, minor fixes. V3: integrate vram offset fixes for APUs V4: enable 2 level VM PTs V5: index SH_MEM_* regs properly V6: add ib_parse() Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: Add support for CIK GPU reset (v2)Alex Deucher1-0/+80
v2: split soft reset into compute and gfx. Still need to make reset more fine grained, but this should be a start. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add gpu init support for CIK (v9)Alex Deucher1-0/+253
v2: tiling fixes v3: more tiling fixes v4: more tiling fixes v5: additional register init v6: rebase v7: fix gb_addr_config for KV/KB v8: drop wip KV bits for now, add missing config reg v9: fix cu count on Bonaire Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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