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path: root/drivers/gpu/drm/radeon/cik.c
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2013-08-31drm/radeon: update line buffer allocation for dce8Alex Deucher1-7/+22
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce8 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-31drm/radeon/cik: properly set up the clearstate buffer for pg (v2)Alex Deucher1-1/+92
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI+. v2: fix addresses Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: fixes for gfx clockgating on CIKAlex Deucher1-10/+5
Clockgating requires signalling between the CP and the RLC to work properly. Resetting the CP block in the CP resume code messed up the internal coordination between the blocks. Removing the reset allows gfx clockgating to work properly. However, when gfx clock gating is enabled, there is a strange interaction with dpm which causes the chip to stay in the high performance level all the time, so leave gfx clockgating disabled for now. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: restructure cg/pg on cik (v2)Alex Deucher1-67/+98
- use new cg/pg flags for finer grained clock and powergating control - restructure the cg/pg code so it can be called from other components such as dpm v2: fix build breakage from rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add audio support for DCE6/8 GPUs (v12)Alex Deucher1-0/+5
Similar to DCE4/5, but supports multiple audio pins which can be assigned per afmt block. v2: rework the driver to handle more than one audio pin. v3: try different dto reg v4: properly program dto v5 (ck): change dto programming order v6: program speaker allocation block v7: rebase v8: rebase on Rafał's changes v9: integrated Rafał's comments, update to latest drm_edid_to_speaker_allocation API v10: add missing line break in error message v11: add back audio enabled messages v12: fix copy paste typo in r600_audio_enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Rafał Miłecki <zajec5@gmail.com>
2013-08-31drm/radeon: separate DMA codeChristian König1-726/+10
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: separate UVD code v3Christian König1-37/+4
Our different hardware blocks are actually completely separated, so it doesn't make much sense any more to structure the code by pure chipset generations. Start restructuring the code by separating our the UVD block. v2: updated commit message v3: rebased and restructurized start/stop functions for kv dpm. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: remove special handling for the DMA ringChristian König1-12/+8
Now that we have callbacks for [rw]ptr handling we can remove the special handling for the DMA rings and use the callbacks instead. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: rework UVD writeback & [rw]ptr handlingChristian König1-2/+1
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/dpm: implement UVD powergating for KB/KVAlex Deucher1-2/+2
Powergate the UVD block when not in use to save power. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: restructure UVD code to handle UVD PG (v2)Alex Deucher1-9/+5
When we PG (powergate) UVD, we need to re-initialize it before we can use it again. v2: rebase on UVD stop fixes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher1-6/+35
This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/kms: add dpm support for KB/KVAlex Deucher1-3/+27
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher1-0/+37
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: add rlc helpers for DPMAlex Deucher1-0/+29
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher1-21/+1454
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher1-5/+5
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: restructure rlc setupAlex Deucher1-30/+54
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: add support for ASPM on CIK asicsAlex Deucher1-0/+151
Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: add support for pcie gen1/2/3 switchingAlex Deucher1-0/+161
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: switch CIK to use radeon_ucode.hAlex Deucher1-16/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/kms: fix up dce8 display watermark calc for dpmAlex Deucher1-22/+74
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-08drm/radeon/cik: use a mutex to properly lock srbm instanced registersAlex Deucher1-0/+10
We need proper locking in the driver when accessing instanced registers on CIK. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-08drm/radeon: only save UVD bo when we have open handlesChristian König1-1/+1
Otherwise just reinitialize from scratch on resume, and so make it more likely to succeed. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-08drm/radeon: always program the MC on startupAlex Deucher1-1/+2
For r6xx+ asics. This mirrors the behavior of pre-r6xx asics. We need to program the MC even if something else in startup() fails. Failure to do so results in an unusable GPU. Based on a fix from: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-08drm/radeon: fix halting UVDChristian König1-1/+2
Removing the clock/power or resetting the VCPU can cause hangs if that happens in the middle of a register write. Stall the memory and register bus before putting the VCPU into reset. Keep it in reset when unloading the module or suspending. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-23drm/radeon: s/drm_order/order_base_2/Daniel Vetter1-7/+7
Last driver and pretty obviously a major user of this little function. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2013-07-14drm/radeon: never unpin UVD bo v3Christian König1-1/+1
Changing the UVD BOs offset on suspend/resume doesn't work because the VCPU internally keeps pointers to it. Just keep it always pinned and save the content manually. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66425 v2: fix compiler warning v3: fix CIK support Note: a version of this patch needs to go to stable. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14drm/radeon: add fault decode function for CIKAlex Deucher1-2/+30
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14drm/radeon: use radeon device for request firmwareJerome Glisse1-18/+7
Avoid creating temporary platform device that will lead to issue when several radeon gpu are in same computer. Instead directly use the radeon device for requesting firmware. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: fix typo in cik_select_se_sh()Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add cik tile mode array queryAlex Deucher1-0/+4
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add support for golden register initAlex Deucher1-0/+438
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add support for compute interruptsAlex Deucher1-5/+116
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: fix up ring functions for compute ringsAlex Deucher1-6/+47
The compute rings use RELEASE_MEM rather then EOP packets for writing fences and there is no SYNC_PFP_ME packet on the compute rings. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: switch to type3 nop packet for compute rings (v2)Alex Deucher1-2/+4
Type 2 packets are deprecated on CIK MEC and we should use type 3 nop packets. Setting the count field to the max value (0x3fff) indicates that only one dword should be skipped like a type 2 packet. v2: add comment to code Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon/cik: Add support for compute queues (v4)Alex Deucher1-9/+513
On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: implement simple doorbell page allocatorAlex Deucher1-0/+38
The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add srbm_select functionAlex Deucher1-2/+25
Allows us to select instanced registers based on: - ME (micro engine - Pipe - Queue - VMID Switch MC setup to use this new function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add UVD support for CIK (v3)Christian König1-0/+111
v2: agd5f: fix clock dividers setup for bonaire v3: agd5f: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add pcie_port indirect register accessorsAlex Deucher1-0/+21
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_xclk() callback for CIKAlex Deucher1-0/+22
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update CIK soft resetAlex Deucher1-146/+241
Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_gpu_clock_counter() callback for cikAlex Deucher1-0/+21
Used for GPU clock counter snapshots. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dce8: add support for display watermark setupAlex Deucher1-0/+537
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: fill in startup/shutdown callbacks (v5)Alex Deucher1-0/+336
v2: update to latest driver changes v3: properly tear down vm on suspend v4: fix up irq init ordering v5: remove outdated comment Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-26drm/radeon/cik: add support for doing async VM pt updates (v5)Alex Deucher1-0/+109
Async page table updates using the sDMA engine. sDMA has a special packet for updating entries for contiguous pages that reduces overhead. v2: add support for and use the CP for now. v3: update for 2 level PTs v4: rebase, fix DMA packet v5: switch to using an IB Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: implement async vm_flush for the sDMA (v6)Alex Deucher1-0/+70
Update the page table base address and flush the VM TLB using the sDMA. V2: update for 2 level PTs V3: update vm flush V4: update SH_MEM* regs V5: switch back to old style VM TLB invalidate V6: fix packet formatting Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher1-6/+739
CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: log and handle VM page fault interruptsAlex Deucher1-0/+10
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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