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path: root/drivers/gpu/drm/panel/panel-simple.c
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2017-01-26drm/panel: simple: Specify bus width and flags for EDT displaysStefan Agner1-0/+4
The display has a 18-Bit parallel LCD interface, require DE to be active high and data driven by the controller on falling pixel clock edge (display samples on rising edge). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-26drm/panel: simple: Add Netron DY E231732Maxime Ripard1-0/+26
The E231732 is a 7" panel with a resolution of 1024x600. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [treding@nvidia.com: add missing device tree binding] Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-26drm/panel: simple: Add support for Tianma TM070JDHG30Gary Bisson1-0/+27
The Tianma TM070JDHG30 is a 7" LVDS display with a resolution of 1280x800. http://usa.tianma.com/products-technology/product/tm070jdhg30-00 You can also find this product along with a FT5x06 touch controller from Boundary Devices: https://boundarydevices.com/product/bd070lic2/ Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-26drm/panel: simple: Add support BOE NV101WXMN51Caesar Wang1-0/+45
The BOE NV101WXMN51 is a 10.1" WXGA color active matrix TFT LCD module using amorphous silicon TFT's as an active switching devices. It can be supported by the simple-panel driver. Read the panel default EDID information: EDID MODE DETAILS name = <NULL> pixel_clock = 71900 lvds_dual_channel = 0 refresh = 0 ha = 1280 hbl = 160 hso = 48 hspw = 32 hborder = 0 va = 800 vbl = 32 vso = 3 vspw = 5 vborder = 0 phsync = + pvsync = - x_mm = 0 y_mm = 0 drm_display_mode .hdisplay = 1280 .hsync_start = 1328 .hsync_end = 1360 .htotal = 1440 .vdisplay = 800 .vsync_start = 803 .vsync_end = 808 .vtotal = 832 There are two modes in the EDID: Detailed mode1: Clock 71.900 MHz, 216 mm x 135 mm 1280 1328 1360 1440 hborder 0 800 803 808 832 vborder 0 +hsync -vsync Detailed mode2: Clock 57.500 MHz, 216 mm x 135 mm 1280 1328 1360 1440 hborder 0 800 803 808 832 vborder 0 +hsync -vsync Support both of these modes on the panel. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: simple: Add support for AUO G185HAN01Lucas Stach1-0/+32
This adds support for the AU Optronics G185HAN01 18.5" LVDS FullHD TFT LCD panel, which can be supported by the simple panel driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: simple: Add support for AUO G133HAN01Lucas Stach1-0/+32
This adds support for the AU Optronics G133HAN01 13.3" LVDS FullHD TFT LCD panel, which can be supported by the simple panel driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: simple: Add more properties to Innolux G121I1-L01Lucas Stach1-13/+17
Convert from a single mode to display timings, which allow to describe the minimum/maximium blanking and clock rates, add enable/disable delays and provide the bus format. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: simple: Add bits-per-component for Sharp LQ123P1JX31zain wang1-0/+1
The Sharp LQ123P1JX31 panel support 8 bits per component. Signed-off-by: zain wang <wzz@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: simple: Check against num_timings when setting preferred for timingChen-Yu Tsai1-1/+1
In the loop on .timings, we should check .num_timings to see if it's the only mode specified, not .num_modes, which should be used with .modes. Fixes: cda553725c92 ("drm/panel: simple: Set appropriate mode type") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06drm/panel: Add support for Chunghwa CLAA070WP03XG panelRandy Li1-0/+27
The Chunghwa CLAA070WP03XG is a 7" 1280x800 panel, which can be supported by the simple panel driver. Signed-off-by: Randy Li <ayaka@soulik.info> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19drm/panel: simple: Add NVD9128 as a simple panelFabien Lahoudere1-0/+26
Add New Vision Display 7.0" 800 RGB x 480 TFT LCD panel Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.co.uk> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19drm/panel: simple: Add support for AUO T215HVN01Haixia Shi1-0/+30
The AUO T215HVN01 is a 21.5" FHD (1920x1080) color TFT LCD panel. This panel is used on the Acer Chromebase 21.5-inch All-in-One (DC221HQ). Link to spec: http://www.udmgroup.com/ftp/T215HVN01.0.pdf v2: fix alphabetical order v3: remove minor revision suffix ".0" and add link to spec v4: add dt-binding documentation Signed-off-by: Haixia Shi <hshi@chromium.org> Tested-by: Haixia Shi <hshi@chromium.org> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19drm/panel: simple: Add support for Sharp LQ150X1LG11 panelsGustaf Lindström1-0/+27
The Sharp 15" LQ150X1LG11 panel is an XGA TFT LCD panel. The simple-panel driver is used to get support for essential functionality of the panel. Signed-off-by: Gustaf Lindström <gl@axentia.se> Signed-off-by: Peter Rosin <peda@axentia.se> [treding@nvidia.com: change .bpc from 8 to 6] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16drm/panel: simple: Fix bus_format for the Olimex LCD-OLinuXino-4.3TSJonathan Liu1-1/+1
The format is RGB888 not RGB666. Signed-off-by: Jonathan Liu <net147@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16drm/panel: simple-panel: Add delay timings for Starry KR122EA0SRABrian Norris1-0/+5
Taking our cue from commit a42f6e3f8f03 ("drm/panel: simple: Add delay timing for Sharp LQ123P1JX31"), let's add timings: .prepare = t1 + t3 .enable = t7 .unprepare = t11 + 12 Without this, the panel may not be given enough time to come up. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16drm/panel: simple: Fix bus flags for Ortustech com43h4m85ulcMarek Vasut1-0/+1
This display expects DE pin and data lines to be active high, add the necessary flags. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Thierry Reding <treding@nvidia.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16drm/panel: simple: Add Innolux G101ICE-L01 panelMichael Olbrich1-0/+31
This patch adds support for Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel to the simple-panel driver. Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24drm/panel: simple: Add delay timing for Sharp LQ123P1JX31Yakir Yang1-0/+5
According to page 16 of the Sharp LQ123P1JX31 datasheet, we need to add the missing delay timing. Panel prepare time should be t1 (0.5 to 10 ms) plus t3 (0 to 100 ms), panel enable time should equal to t7 (0 to 50 ms) and panel unprepare time should be t11 (1 to 50 ms) plus t12 (500 ms). Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Starry KR122EA0SRA panelDouglas Anderson1-0/+26
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. EDID shows: Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm 1920 1936 1952 1984 hborder 0 1200 1215 1217 1235 vborder 0 -hsync -vsync Manufacturer-specified data, tag 15 ASCII string: STARRY ASCII string: KR122EA0SRA Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Sharp LQ101K1LY04Joshua Clayton1-0/+27
Add simple-panel support for the Sharp LQ101K1LY04, which is a 10" WXGA (1280x800) LVDS panel. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for LG LP079QX1-SP0V panelYakir Yang1-0/+26
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Sharp LQ123P1JX31 panelYakir Yang1-0/+26
The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Samsung LSN122DL01-C01 panelYakir Yang1-0/+25
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for LG LP097QX1-SPA1 panelYakir Yang1-0/+25
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Update backlight state propertyThierry Reding1-0/+2
Some backlight drivers ignore the power property and instead only use the state property. Fixup the panel driver to set the state property in addition to the power property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-13drm/panel: simple: Remove gratuitous blank lineThierry Reding1-1/+0
This blank line was introduced in commit c8521969dea2 ("drm/panel: simple: Add support for BOE TV080WUM-NL0"), likely by mistake. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-10drm/panel: simple: Fix a couple of physical sizesThierry Reding1-4/+4
Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the horizontal and vertical resolutions in the size.width and size.height fields, whereas they should contain the physical dimensions of the panel. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Add support for TPK U.S.A. LLC Fusion 7" and 10.1" panelsBhuvanchandra DV1-0/+51
Add support for TPK U.S.A. LLC Fusion 7", 10.1" panels to the DRM simple panel driver. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Add support for Innolux AT070TN92Riccardo Bortolato1-0/+26
Add support for the Innolux AT070TN92 panel. Signed-off-by: Riccardo Bortolato <bortolato@navaltechitalia.it> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Remove useless drm_mode_set_name()Boris Brezillon1-2/+0
drm_display_mode_from_videomode() already calls drm_mode_set_name() on the provided mode. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [treding@nvidia.com: slightly reword commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Set appropriate mode typeBoris Brezillon1-0/+11
All modes exposed by simple panels should be tagged as driver defined modes. Moreover, if a panel supports only one mode, this mode is obviously the preferred one. Doing this also fix a problem occurring when a 'video=' parameter is passed on the kernel command line. In some cases the user provided mode will be preferred over the simple panel ones, which might result in unpredictable behavior. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com> [treding@nvidia.com: reshuffle some code for consistency] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TSMaxime Ripard1-0/+26
Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple panel driver. It is a 480x272 panel connected through a 24-bits RGB interface. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12drm/panel: simple: Add the 7" DPI panel from AdafruitEric Anholt1-0/+37
This is a basic TFT panel with a 40-pin FPC connector on it. The specification doesn't define timings, but the Adafruit instructions were setting up 800x480 CVT. v2: Add .bus_format and vsync/hsync flags. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org> [treding@nvidia.com: keep entries properly sorted] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-05drm/fsl-dcu: use bus_flags for pixel clock polarityStefan Agner1-1/+2
The drivers current default configuration drives the pixel data on rising edge of the pixel clock. However, most display sample data on rising edge... This leads to color shift artefacts visible especially at edges. This patch changes the relevant defines to be useful and actually set the bits, and changes pixel clock polarity to drive the pixel data on falling edge by default. The patch also adds an explicit pixel clock polarity flag to the display introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to retain the initial behavior. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-05-05drm: introduce bus_flags in drm_display_infoStefan Agner1-0/+2
Introduce bus_flags to specify display bus properties like signal polarities. This is useful for parallel display buses, e.g. to specify the pixel clock or data enable polarity. Suggested-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Manfred Schlaegl <manfred.schlaegl@gmx.at> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-03-17Merge tag 'drm/panel/for-4.6-rc1' of ↵Dave Airlie1-0/+81
http://anongit.freedesktop.org/git/tegra/linux into drm-next drm/panel: Changes for v4.6-rc1 This contains a refactoring of parts of the DSI core to allow creating DSI devices from non-DSI control busses (i.e. I2C, SPI, ...). Other than that there's support for a couple of new panels as well as a few cleanup patches. * tag 'drm/panel/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux: drm/bridge: Make (pre/post) enable/disable callbacks optional drm/panel: simple: Add URT UMSH-8596MD-xT panels support dt-bindings: Add URT UMSH-8596MD-xT panel bindings of: Add United Radiant Technology Corporation vendor prefix drm/panel: simple: Support for LG lp120up1 panel dt-bindings: Add LG lp120up1 panel bindings drm/panel: simple: Fix g121x1_l03 hsync/vsync polarity drm/dsi: Get DSI host by DT device node drm/dsi: Add routine to unregister a DSI device drm/dsi: Try to match non-DT DSI devices drm/dsi: Use mipi_dsi_device_register_full() for DSI device creation drm/dsi: Check for CONFIG_OF when defining of_mipi_dsi_device_add()
2016-03-02drm/panel: simple: Add URT UMSH-8596MD-xT panels supportMaciej S. Szmigiero1-0/+54
Add support for United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panels in the simple-panel driver. Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-02drm/panel: simple: Support for LG lp120up1 panelJitao Shi1-0/+26
The LG lp120up1 TFT LCD panel with eDP interface is a 12.0" 1920x1280 panel, which can be supported by the simple panel driver. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-02drm/panel: simple: Fix g121x1_l03 hsync/vsync polarityAkshay Bhat1-0/+1
Set hsync/vsync to active low for g121x1_l03 panel to match the recommended setting in the datasheet. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-26drm/fsl-dcu: use mode flags for hsync/vsync polarityStefan Agner1-0/+1
The current default configuration is as follows: - Invert VSYNC signal (active LOW) - Invert HSYNC signal (active LOW) The mode flags allow to specify the required polarity per mode. Furthermore, none of the current driver settings is actually a standard polarity. This patch applies the current driver default polarities as explicit flags to the display which has been introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now also parses the flags field and applies the configuration accordingly, by using the following values as standard polarities: (e.g. when no flags are specified): - VSYNC signal not inverted (active HIGH) - HSYNC signal not inverted (active HIGH) Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-12-16drm/panel: simple: Add QiaoDian qd43003c0-40Josh Wu1-0/+27
The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel. Timings from the OTA5180A document, ver 0.9, section 10.1.1: http://www.orientdisplay.com/pdf/OTA5180A.pdf Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16drm/panel: add kernel doc for size attributes in panel_descUlrich Ölmann1-0/+4
Document that 'width' and 'height' are measured in millimeters. Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16drm/panel: simple: Add support for Kyocera TCG121XGLP panelLucas Stach1-0/+27
The Kyocera TCG121XGLP panel is an XGA LCD TFT panel connected through LVDS, which can be supported by the simple panel driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23drm/panel: simple: Add support for Innolux G121X1-L03Akshay Bhat1-0/+31
Add support for Innolux CheMei 12" G121X1-L03 XGA LVDS display. Datasheet: http://www.azdisplays.com/PDF/G121X1-L03.pdf Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23drm/panel: simple: Add support for BOE TV080WUM-NL0Chris Zhong1-0/+34
The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel connected using four DSI lanes. It can be supported by the simple-panel driver. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14drm/panel: Add display timing for Okaya RS800480T-7X0GPGary Bisson1-0/+33
Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14drm/panel: simple: Add support for NEC NL4827HC19-05B 480x272 paneljianwei wang1-0/+27
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM simple panel driver. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> [treding@nvidia.com: add .bpc field for panel] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14drm/panel: simple: Add support for AUO B080UAN01Thierry Reding1-0/+31
The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four DSI lanes. It can be supported by the simple-panel driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14drm/panel: simple: Correct minimum hsync length of the HannStar HSD070PWW1 panelPhilipp Zabel1-1/+6
According to the data sheet, the minimum horizontal blanking interval is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the minimum working horizontal blanking interval to be 60 clocks. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panelPhilipp Zabel1-0/+1
The bus format both specifies the bpc and the way the individual bits get serialized into the 7 LVDS timeslots. While the is only one standard mapping for 6 bpc and so the driver could infer the bit mapping from the bpc alone, there are more options for the 8 bpc case which makes specifiying the bus format mandatory. To keep things consistent across panels and to set a precedent for new panel additions add the proper bus format. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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