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path: root/drivers/gpu/drm/nouveau/nv50_pm.c
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2013-11-08drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERMBen Skeggs1-855/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nv04/disp: hide all the cruft away in its own little holeBen Skeggs1-1/+1
It'd be pretty awesome if someone would care enough to port this all properly to a class interface, perhaps submitting a command stream to the core via a sw object on PFIFO (emulating how EVO works basically, and also what nvidia have done forever..).. But, this seems unlikely given how old this hardware is now, so, lets just hide it away. There's a heap of other bits and pieces laying around that are still tangled. I'll (re)move them in pieces. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nv50-nvc0: switch to common disp impl, removing previous versionBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-04Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds1-139/+108
Pull drm merge (part 1) from Dave Airlie: "So first of all my tree and uapi stuff has a conflict mess, its my fault as the nouveau stuff didn't hit -next as were trying to rebase regressions out of it before we merged. Highlights: - SH mobile modesetting driver and associated helpers - some DRM core documentation - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write combined pte writing, ilk rc6 support, - nouveau: major driver rework into a hw core driver, makes features like SLI a lot saner to implement, - psb: add eDP/DP support for Cedarview - radeon: 2 layer page tables, async VM pte updates, better PLL selection for > 2 screens, better ACPI interactions The rest is general grab bag of fixes. So why part 1? well I have the exynos pull req which came in a bit late but was waiting for me to do something they shouldn't have and it looks fairly safe, and David Howells has some more header cleanups he'd like me to pull, that seem like a good idea, but I'd like to get this merge out of the way so -next dosen't get blocked." Tons of conflicts mostly due to silly include line changes, but mostly mindless. A few other small semantic conflicts too, noted from Dave's pre-merged branch. * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits) drm/nv98/crypt: fix fuc build with latest envyas drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering drm/nv41/vm: fix and enable use of "real" pciegart drm/nv44/vm: fix and enable use of "real" pciegart drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie drm/nouveau: store supported dma mask in vmmgr drm/nvc0/ibus: initial implementation of subdev drm/nouveau/therm: add support for fan-control modes drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules drm/nouveau/therm: calculate the pwm divisor on nv50+ drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster drm/nouveau/therm: move thermal-related functions to the therm subdev drm/nouveau/bios: parse the pwm divisor from the perf table drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices drm/nouveau/therm: rework thermal table parsing drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table drm/nouveau: fix pm initialization order drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it drm/nouveau: log channel debug/error messages from client object rather than drm client drm/nouveau: have drm debugging macros build on top of core macros ...
2012-10-03drm/nouveau/therm: move thermal-related functions to the therm subdevMartin Peres1-58/+0
It looks scary because of the size, but I tried to keep the differences minimal. Further patches will fix the actual "driver" code and add new features. v2: change filenames, split to submodules v3: add a missing include v4: Ben Skeggs <bskeggs@redhat.com> - fixed set_defaults() to allow min_duty < 30 (thermal table will override this if it's actually necessary) - fixed set_defaults() to not provide pwm_freq so nv4x (which only has pwm_div) can actually work. the boards using pwm_freq will have a thermal table entry to provide us the value. - removed unused files Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: port remainder of drm code, and rip out compat layerBen Skeggs1-86/+115
v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: port all engines to new engine module formatBen Skeggs1-1/+0
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fb: merge fb/vram and port to subdev interfacesBen Skeggs1-3/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/clock: pull in the implementation from all over the placeBen Skeggs1-6/+6
Still missing the main bits we use to change performance levels, I'll get to it after all the hard yakka has been finished. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs1-1/+1
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-02UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/David Howells1-1/+1
Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
2012-03-13drm/nv50/hwsq: some nv92 fixesMartin Peres1-2/+3
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: wait for all fifo-connected engines to idle before reclockingMartin Peres1-0/+2
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: use hwsq for engine reclocking tooBen Skeggs1-87/+98
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/disp: more accurate function to determine active crtcsBen Skeggs1-8/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: initial work towards proper memory reclocking, with timingsBen Skeggs1-46/+154
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-02-01drm/nv50/pm: signedness bug in nv50_pm_clocks_pre()Dan Carpenter1-2/+2
calc_mclk() returns zero on success and negative on failure but clk is a u32. v2: Martin Peres: - clk should be an int, not a u32 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: just pass gpio line to pwm_*, not entire gpio structBen Skeggs1-12/+9
We don't need more than the line id to determine the PWM controller, and the GPIO interfaces are about to change somewhat. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/hwsq: remove some magic, give proper opcode namesBen Skeggs1-4/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: introduce hwsq-based memory reclockingMartin Peres1-62/+145
More work needs to be done on supporting the different memory types. v2 (Ben Skeggs): - fixed up conflicts from not having pausing patch first - restructured code somewhat to fit with how all the other code works - fixed bug where incorrect mpll_ctrl could get set sometimes - removed stuff that's cargo-culted from the binary driver - merged nv92+ display disable into hwsq - fixed incorrect opcode 0x5f magic at end of ucode Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: fix a typo in clock calculationMartin Peres1-1/+1
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: only touch 0x611200 on nv92-Ben Skeggs1-3/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: stabilise transition to 100MHz mclk a bitBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: avoid touching dom6/vdec clocks if perflvl doesn't define itBen Skeggs1-16/+16
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: fix thinko which lead to clocks being slightly off sometimesBen Skeggs1-22/+24
read_pll_ref() needs to take into account the refclk src bits in 0xc040 on some chipsets, it wasn't doing this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: 0x84/0x86 can't use "1" for nvclk src, need 0x50 methodBen Skeggs1-2/+5
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: free state struct after setting clocksBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: rewrite clock management, and switch to the new pm hooksBen Skeggs1-90/+568
This area is horrifically complicated on these chipsets, and it's likely we will need at least a few more tweaks yet. Oh yes, and it's completely disabled on IGPs for the moment. From traces, things look potentially different there yet again. Sigh... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: convert to new fanspeed pwm controller hooksBen Skeggs1-61/+33
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: mostly nailed down fan pwm frequency selectionBen Skeggs1-1/+11
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: add support for pwm fan controlBen Skeggs1-0/+74
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nouveau/bios: allow passing in crtc to the init table parserBen Skeggs1-4/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: improve nv50_pm_get_clock()Emil Velikov1-0/+15
Many of the nv50 cards have their shader and/or memory pll disabled at some stage. This patch addresses those cases, so that the function returns the correct frequency. When the shader pll is disabled, the blob reports 2*core clock Whereas for memory, the data stored in the vbios. This action is incorrect as some vbioses store a clock value that is less than the refference clock of the pll. Thus we are reporting the reff_clk as it is the frequency the pll actually operates v2 - Convert NV_INFO() messages to NV_DEBUG() Provide more information in the actuall message Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nva3: split pm backend out from nv50Ben Skeggs1-37/+19
This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nouveau: run perflvl and M table scripts on mem clock changeBen Skeggs1-0/+22
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nouveau: pass perflvl struct to clock_pre()Ben Skeggs1-1/+2
On certain boards, there's BIOS scripts and memory timings that need to be modified with the memclk. Just pass in the entire perflvl struct and let the chipset-specific code decide what to do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: allow static performance level settingBen Skeggs1-1/+1
Guarded by a module parameter for the moment, read the code for the magic value which enables it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nv50: import initial clock get/set routines + hook up pm engineBen Skeggs1-0/+126
This will make nouveau_pm attempt to report the card's current performance level both during bootup, and through sysfs. This is a very initial implementation, and can be improved a *lot* Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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