summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
AgeCommit message (Expand)AuthorFilesLines
2011-12-21drm/nouveau: Fix pushbufs over the 4GB mark.Francisco Jerez1-2/+4
2011-02-24drm/nv50: drop explicit yields in favour of smaller PFIFO timesliceBen Skeggs1-1/+2
2010-12-08drm/nv50: import new vm codeBen Skeggs1-1/+2
2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs1-0/+9
2010-12-03drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs1-0/+4
2010-12-03drm/nouveau: Refactor context destruction to avoid a lock ordering issue.Francisco Jerez1-0/+17
2010-12-03drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs1-4/+5
2010-11-18drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs1-0/+5
2010-09-24drm/nouveau: tidy ram{ht,fc,ro} a bitBen Skeggs1-1/+1
2010-09-24drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanityBen Skeggs1-43/+42
2010-09-24drm/nouveau: rebase per-channel pramin heap offsets to 0Ben Skeggs1-8/+8
2010-09-24drm/nouveau: modify object accessors, offset in bytes rather than dwordsBen Skeggs1-105/+106
2010-07-13drm/nv50: fix RAMHT sizeBen Skeggs1-1/+3
2010-07-13drm/nv50: cleanup nv50_fifo.cBen Skeggs1-67/+40
2010-07-13drm/nouveau: add instmem flush() hookBen Skeggs1-12/+3
2010-02-25drm/nv50: switch to indirect push buffer controlsBen Skeggs1-4/+4
2010-02-25drm/nouveau: protect channel create/destroy and irq handler with a spinlockMaarten Maathuis1-0/+5
2010-02-10drm/nv50: delete ramfc object after disabling fifo, not beforeMaarten Maathuis1-3/+6
2010-01-18drm/nv50: fix alignment of per-channel fifo cacheBen Skeggs1-1/+1
2010-01-11drm/nv50: restore correct cache1 get/put address on fifoctx loadBen Skeggs1-4/+2
2009-12-16drm/nv50: fix two potential suspend/resume oopsesBen Skeggs1-1/+1
2009-12-11drm/nouveau: Add DRM driver for NVIDIA GPUsBen Skeggs1-0/+494
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-30 21:50:42 +0300