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path: root/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
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2021-06-23drm/msm: Generated register updateRob Clark1-13/+21
Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5 Small bit of .c churn in the phy code to adapt to split up of phy related registers. Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: sync generated headersRob Clark1-13/+13
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2018-08-11drm/msm: update generated headersRob Clark1-13/+13
Resync generated headers to pull in a6xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: update generated headersRob Clark1-21/+47
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: update generated headersRob Clark1-1/+1
Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-03-03drm/msm: update generated headersRob Clark1-2/+12
Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Update generated headers for HDMI 8996 PHYArchit Taneja1-2/+498
Adds HDMI 8996 PHY offsets. The offsets are divided into 3 parts: - Core HDMI PHY registers - HDMI PLL registers (part of QSERDES block) - HDMI TX lane registers (part of QSERDES block) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Update generated headers to split PHY/PLL offsetsArchit Taneja1-83/+74
- Create separate domains for 8960 PHY and PLL - Create separate domains for 8x60 PHY Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm: update generated headersRob Clark1-4/+4
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-16drm/msm: update generated headersRob Clark1-11/+17
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: update generated headersRob Clark1-6/+93
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-02-01drm/msm: update generated headersRob Clark1-12/+94
Resync from rnndb database, to pull in register defines for: * eDP * HDMI/HDCP * mdp4/mdp5 YUV support * mdp5 hw cursor support Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: update generated headersRob Clark1-4/+4
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-09-10drm/msm: update generated headersRob Clark1-5/+5
In particular, pick up the definitions for a handful of LVDS related registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-08-04drm/msm: update generated headersRob Clark1-6/+103
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09drm/msm: resync generated headersRob Clark1-8/+75
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-01drm/msm: resync generated headersRob Clark1-3/+3
resync to latest envytools db, fixes a typo: s/mpd4/mdp4/ Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
2013-08-24drm/msm: add register definitionsRob Clark1-0/+508
Generated from rnndb files in: https://github.com/freedreno/envytools Keep this split out as a separate commit to make it easier to review the actual driver. Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 11:17:15 +0300