summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/msm/adreno
AgeCommit message (Collapse)AuthorFilesLines
2024-08-03drm/msm/a6xx: Fix A702 UBWC modeKonrad Dybcio1-1/+1
[ Upstream commit 593f1dd4c81f6932042508a80186dbdea90312a5 ] UBWC_MODE is a one-bit-wide field, so a value of 2 is obviously bogus. Replace it with the correct value (0). Fixes: 18397519cb62 ("drm/msm/adreno: Add A702 support") Reported-by: Connor Abbott <cwabbott0@gmail.com> Closes: https://lore.kernel.org/linux-arm-msm/CACu1E7FTN=kwaDJMNiTmFspALzj2+Q-nvsN5ugi=vz4RdUGvGw@mail.gmail.com/ Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/597359/ Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-08-03drm/msm/a6xx: use __unused__ to fix compiler warnings for gen7_* includesAbhinav Kumar1-8/+5
[ Upstream commit 71d9b458b2bfe79197194d914aa9bada46fb9e14 ] GCC diagnostic pragma method throws below warnings in some of the versions drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:16:9: warning: unknown option after '#pragma GCC diagnostic' kind [-Wpragmas] #pragma GCC diagnostic ignored "-Wunused-const-variable" ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:18:0: drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h:924:19: warning: 'gen7_0_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_0_0_external_core_regs[] = { ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:19:0: drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h:748:19: warning: 'gen7_2_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_2_0_external_core_regs[] = { ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:20:0: drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h:1188:43: warning: 'gen7_9_0_sptp_clusters' defined but not used [-Wunused-variable] static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { ^ drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h:1438:19: warning: 'gen7_9_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_9_0_external_core_regs[] = { Remove GCC version dependency by using __unused__ for the unused gen7_* includes. Changes in v2: - Fix the warnings in the commit text - Use __attribute((__unused__)) instead of local assignment changes in v3: - drop the Link from the auto add changes in v4: - replace __attribute((__unused__)) with __always_unused Fixes: 64d6255650d4 ("drm/msm: More fully implement devcoredump for a7xx") Suggested-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/597265/ [Add gen7_9_0_cx_debugbus_blocks as well] Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-05-07drm/msm/a6xx: Cleanup indexed regs const'nessRob Clark2-10/+13
These tables were made non-const in commit 3cba4a2cdff3 ("drm/msm/a6xx: Update ROQ size in coredump") in order to avoid powering up the GPU when reading back a devcoredump. Instead let's just stash the count that is potentially read from hw in struct a6xx_gpu_state_obj, and make the tables const again. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/592699/
2024-05-05drm/msm: Add devcoredump support for a750Connor Abbott1-18/+46
Add an a750 case to the various places where we choose a list of registers. Patchwork: https://patchwork.freedesktop.org/patch/592519/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592519 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-05drm/msm: Adjust a7xx GBIF debugbus dumpingConnor Abbott2-4/+4
Use the kgsl-style list of indices, because this is about to change for a750 and we want to reuse the downstream header directly. Patchwork: https://patchwork.freedesktop.org/patch/592520/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592520 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-05drm/msm: Fix imported a750 snapshot header for upstreamConnor Abbott1-434/+454
Add A7XX prefixes necessary because we use the same code for dumping a6xx and a7xx, fix register name prefixes for upstream, and use the upstream header. Patchwork: https://patchwork.freedesktop.org/patch/592517/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592517 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm: Import a750 snapshot registers from kgslConnor Abbott1-0/+1426
Import from kgsl commit 809ee24fe560. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592516/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting failsKonrad Dybcio1-1/+2
Calling a6xx_destroy() before adreno_gpu_init() leads to a null pointer dereference on: msm_gpu_cleanup() : platform_set_drvdata(gpu->pdev, NULL); as gpu->pdev is only assigned in: a6xx_gpu_init() |_ adreno_gpu_init |_ msm_gpu_init() Instead of relying on handwavy null checks down the cleanup chain, explicitly de-allocate the LLC data and free a6xx_gpu instead. Fixes: 76efc2453d0e ("drm/msm/gpu: Fix crash during system suspend after unbind") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/588919/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/adreno: fix CP cycles stat retrieval on a7xxZan Dobersek1-2/+2
a7xx_submit() should use the a7xx variant of the RBBM_PERFCTR_CP register for retrieving the CP cycles value before and after the submitted command stream execution. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Patchwork: https://patchwork.freedesktop.org/patch/588445/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/a7xx: allow writing to CP_BV counter selection registersZan Dobersek1-4/+4
In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling purposes of tools like fdperf and perfetto. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Patchwork: https://patchwork.freedesktop.org/patch/580548/ [fixup a730_protect size] Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-04-22drm/msm: Drop msm_read/writelKonrad Dybcio4-11/+11
Totally useless. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Patchwork: https://patchwork.freedesktop.org/patch/588804/ Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm: drop A6xx headerDmitry Baryshkov1-9380/+0
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A6xx header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585868/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-18-4bdb277a85a1@linaro.org
2024-04-22drm/msm: drop C++ parts of a6xx.xml.hDmitry Baryshkov1-2478/+0
As a preparation to removal of a6xx.xml.h, drop the C++ part of the heder, it is not used by the kernel anyway. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585866/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-17-4bdb277a85a1@linaro.org
2024-04-22drm/msm: drop A6xx GMU headerDmitry Baryshkov1-422/+0
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A6xx GMU header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585870/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-16-4bdb277a85a1@linaro.org
2024-04-22drm/msm: drop A5xx headerDmitry Baryshkov1-5572/+0
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A5xx header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585865/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-15-4bdb277a85a1@linaro.org
2024-04-22drm/msm: drop A3xx and A4xx headersDmitry Baryshkov2-7647/+0
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A3xx and A4xx headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585869/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-14-4bdb277a85a1@linaro.org
2024-04-22drm/msm: drop A2xx and common headersDmitry Baryshkov3-6593/+0
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A2xx and common headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585861/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-13-4bdb277a85a1@linaro.org
2024-04-22drm/msm: move msm_gpummu.c to adreno/a2xx_gpummu.cDmitry Baryshkov3-2/+130
The msm_gpummu.c implementation is used only on A2xx and it is tied to the A2xx registers. Rename the source file accordingly. Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585846/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-4-4bdb277a85a1@linaro.org
2024-04-05drm/msm/adreno: Set highest_bank_bit for A619Luca Weiss1-0/+4
The default highest_bank_bit of 15 didn't seem to cause issues so far but downstream defines it to be 14. But similar to [0] leaving it on 14 (or 15 for that matter) causes some corruption issues with some resolutions with DisplayPort, like 1920x1200. So set it to 13 for now so that there's no screen corruption. [0] commit 6a0dbcd20ef2 ("drm/msm/a6xx: set highest_bank_bit to 13 for a610") Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Patchwork: https://patchwork.freedesktop.org/patch/585215/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-04-05drm/msm: fix the `CRASHDUMP_READ` target of `a6xx_get_shader_block()`Miguel Ojeda1-1/+1
Clang 14 in an (essentially) defconfig arm64 build for next-20240326 reports [1]: drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:843:6: error: variable 'out' set but not used [-Werror,-Wunused-but-set-variable] The variable `out` in these functions is meant to compute the `target` of `CRASHDUMP_READ()`, but in this case only the initial value (`dumper->iova + A6XX_CD_DATA_OFFSET`) was being passed. Thus use `out` as it was intended by Connor [2]. There was an alternative patch at [3] that removed the variable altogether, but that would only use the initial value. Fixes: 64d6255650d4 ("drm/msm: More fully implement devcoredump for a7xx") Closes: https://lore.kernel.org/lkml/CANiq72mjc5t4n25SQvYSrOEhxxpXYPZ4pPzneSJHEnc3qApu2Q@mail.gmail.com/ [1] Link: https://lore.kernel.org/lkml/CACu1E7HhCKMJd6fixZSPiNAz6ekoZnkMTHTcLFVmbZ-9VoLxKg@mail.gmail.com/ [2] Link: https://lore.kernel.org/lkml/20240307093727.1978126-1-colin.i.king@gmail.com/ [3] Signed-off-by: Miguel Ojeda <ojeda@kernel.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/584955/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm/adreno: Add A702 supportKonrad Dybcio3-9/+117
The A702 is a weird mix of 600 and 700 series.. Perhaps even a testing ground for some A7xx features with good ol' A6xx silicon. It's basically A610 that's been beefed up with some new registers and hw features (like APRIV!), that was then cut back in size, memory bus and some other ways. Add support for it, tested with QCM2290 / RB1. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579752/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm: Fix page fault client detection on a660 family and a7xxConnor Abbott1-10/+85
Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/575918/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm: More fully implement devcoredump for a7xxConnor Abbott4-632/+1462
Use the vendor-provided snapshot headers to dump the contextless registers, shader blocks, and cluster registers. Still unimplemented are the GMU registers and "external core" registers, which would require more work because they use register spaces we don't have described in devicetree and dump registers from multiple spaces in a single list. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/575919/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm: Fix snapshotting a7xx indexed regsConnor Abbott1-2/+2
We were overwriting the last indexed reg (CP_ROQ) and we were snapshotting the same CP_MEMPOOL block twice instead of snapshotting CP_BV_MEMPOOL as intended. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/575920/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm: Import a7xx crashdump register lists from kgslConnor Abbott2-0/+1681
This imports these files as-is, the following commits will have to make slight changes to get them to compile because downstream uses un-namespaced enums that conflict with a6xx. However we should try as much as possible to stick to downstream's format to make importing new gens easier. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/575921/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm: add support for A750 GPUNeil Armstrong4-5/+49
Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578693/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm/adreno: Add A305B supportLuca Weiss3-7/+26
Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: David Heidelberg <david@ixit.cz> Patchwork: https://patchwork.freedesktop.org/patch/575274/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm/a7xx: Fix LLC typoRob Clark1-1/+1
We'd miss actually activating LLC. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Patchwork: https://patchwork.freedesktop.org/patch/573043/
2024-02-26drm/msm/adreno: Update generated headersRob Clark9-1738/+5589
This updates the GPU headers to latest from mesa, using gen_header.py (which is used to generate headers at bulid time for mesa), rather than headergen2 (which doesn't have proper support for A6XX vs A7XX register variants). Mostly just uninteresting churn, but there are a couple spots in a7xx paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are a7xx specific. Cc: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/574880/
2024-02-26drm/msm/adreno: Add support for SM7150 SoC machineDanila Tikhonov1-0/+22
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0, 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up to zero decimal places. Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn). Add this as machine = "qcom,sm7150", because speed-bin values are different from atoll (sc7180/sm7125). Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578902/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-26drm/msm/a6xx: specify UBWC config for sc7180Dmitry Baryshkov1-2/+1
Historically the Adreno driver has not been updating memory configuration registers on a618 (SC7180 platform) implying that the default configuration is fine. After the rework performed in the commit 8814455a0e54 ("drm/msm: Refactor UBWC config setting") the function a6xx_calc_ubwc_config() still contained this shortcut and did not calculate UBWC configuration. However the function which now actually updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such check. Rather than adding the check to a6xx_set_ubwc_config(), fill in the UBWC config for a618 (based on readings from SC7180). Reported-by: Leonard Lausen <leonard@lausen.nl> Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting") Cc: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/579113/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-02-02drm/msm/a6xx: set highest_bank_bit to 13 for a610Dmitry Baryshkov1-1/+1
During the testing of Gnome on Qualcomm Robotics platform screen corruption has been observed. Lowering GPU's highest_bank_bit from 14 to 13 seems to fix the screen corruption. Note, the MDSS and DPU drivers use HBB=1 (which maps to the highest_bank_bit = 14). So this change merely works around the UBWC swizzling issue on this platform until the real cause is found. Fixes: e7fc9398e608 ("drm/msm/a6xx: Add A610 support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/573838/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-12-10drm/msm/adreno: Fix A680 chip idBjorn Andersson1-1/+1
The only A680 referenced from DeviceTree is patch level 1, which since commit '90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU")' isn't a known chip id. Correct the chip id to allow the A680 to be recognized again. Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/569839/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-12-10drm/msm: Add param for the highest bank bitConnor Abbott1-0/+3
This parameter is programmed by the kernel and influences the tiling layout of images. Exposing it to userspace will allow it to tile/untile images correctly without guessing what value the kernel programmed, and allow us to change it in the future without breaking userspace. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/571181/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-12-10drm/msm: Refactor UBWC config settingConnor Abbott3-53/+78
Split up calculating configuration parameters and programming them, so that we can expose them to userspace. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/571180/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-12-10Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark1-2/+4
Backmerge drm-misc-next to pick up some dependencies for drm/msm patches, in particular: https://patchwork.freedesktop.org/patch/570219/?series=127251&rev=1 https://patchwork.freedesktop.org/series/123411/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-11-25drm/msm/a690: Fix reg values for a690Danylo Piliaiev1-10/+13
KGSL doesn't support a690 so all reg values were the same as on a660. Now we know the values and they are different from the windows driver. This fixes hangs on D3D12 games and some CTS tests. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/568931/
2023-11-25drm/msm/a6xx: Add missing BIT(7) to REG_A6XX_UCHE_CLIENT_PFDanylo Piliaiev1-1/+1
Downstream always set BIT(7) Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/568930/
2023-11-15Merge drm/drm-next into drm-misc-nextMaxime Ripard11-130/+1049
Let's kickstart the v6.8 release cycle. Signed-off-by: Maxime Ripard <mripard@kernel.org>
2023-11-02drm/sched: Add drm_sched_wqueue_* helpersMatthew Brost1-2/+4
Add scheduler wqueue ready, stop, and start helpers to hide the implementation details of the scheduler from the drivers. v2: - s/sched_wqueue/sched_wqueue (Luben) - Remove the extra white line after the return-statement (Luben) - update drm_sched_wqueue_ready comment (Luben) Cc: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Link: https://lore.kernel.org/r/20231031032439.1558703-2-matthew.brost@intel.com Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
2023-10-23Merge tag 'drm-msm-next-2023-10-17' of ↵Dave Airlie11-130/+1049
https://gitlab.freedesktop.org/drm/msm into drm-next Updates for v6.7 DP: - use existing helpers for DPCD handling instead of open-coded functions - set the subconnector type according to the plugged cable / dongle skip validity check for DP CTS EDID checksum DPU: - continued migration of feature flags to use core revision checks - reworked interrupts code to use '0' as NO_IRQ, removed raw IRQ indices from log / trace output gpu: - a7xx support (a730, a740) - fixes and additional speedbins for a635, a643 core: - decouple msm_drv from kms to more cleanly support headless devices (like imx5+a2xx) From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvzkBL2_OgyOeP_b6rVEjrNdfm8jcKzaB04HqHyT5jYwA@mail.gmail.com Signed-off-by: Dave Airlie <airlied@redhat.com>
2023-10-16drm/msm/a7xx: actually use a7xx state registersDmitry Baryshkov2-10/+17
Make a6xx_get_registers() use a7xx registers instead of a6xx ones if the detected Adreno is from the A7xx family. Fixes: e997ae5f45ca ("drm/msm/a6xx: Mostly implement A7xx gpu_state") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/562233/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-16drm/msm/a6xx: Fix up QMP handlingKonrad Dybcio1-6/+12
The commit referenced in the Fixes tag had a couple problems (as pointed out by Dan): - qmp_put was never called, resulting in refcnt leaks - failling to acquire the QMP mailbox on A7xx would not undo the probe function properly - the qmp_put call present in the code was unreachable Fix all of these issues. Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Fixes: 88a0997f2f94 ("drm/msm/a6xx: Send ACD state to QMP at GMU resume") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/562761/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/adreno: Add A635 speedbin 0xac (A643)Konrad Dybcio1-0/+1
Downstream calls this the "speedbin 1", but that number is already occupied. Use index two. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559607/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/adreno: Add ZAP firmware name to A635Konrad Dybcio1-0/+1
Some (many?) devices with A635 expect a ZAP shader to be loaded. Set the file name to allow for that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559605/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/a6xx: Fix unknown speedbin caseKonrad Dybcio1-1/+1
When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559604/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/adreno: Fix SM6375 GPU IDKonrad Dybcio1-1/+1
SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that. Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/554527/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/a6xx: Poll for GBIF unhalt status in hw_initKonrad Dybcio1-0/+4
Some GPUs - particularly A7xx ones - are really really stubborn and sometimes take a longer-than-expected time to finish unhalting GBIF. Note that this is not caused by the request a few lines above. Poll for the unhalt ack to make sure we're not trying to write bits to an essentially dead GPU that can't receive data on its end of the bus. Failing to do this will result in inexplicable GMU timeouts or worse. This is a rather ugly hack which introduces a whole lot of latency. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559292/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/a6xx: Add A740 supportKonrad Dybcio6-38/+201
A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559291/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-10-09drm/msm/a6xx: Add A730 supportKonrad Dybcio4-4/+203
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559290/ Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-24 12:53:05 +0300