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path: root/drivers/gpu/drm/i915
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2015-07-06drm/i915: intel_frontbuffer_flip_prepare() doesn't need struct_mutexPaulo Zanoni1-1/+1
So release the lock earlier. Reviewed-by: Chris wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: add the FBC mutexPaulo Zanoni5-19/+96
Make sure we're not going to have weird races in really weird cases where a lot of different CRTCs are doing rendering and modesets at the same time. With this change and the stolen_lock from the previous patch, we can start removing the struct_mutex locking we have around FBC in the next patches. v2: - Rebase (6 months later) - Also lock debugfs and stolen. v3: - Don't lock a single value read (Chris). - Replace lockdep assertions with WARNs (Daniel). - Improve commit message. - Don't forget intel_pre_plane_update() locking. v4: - Don't remove struct_mutex at intel_pre_plane_update() (Chris). - Add comment regarding locking dependencies (Chris). - Rebase after the stolen code rework. - Rebase again after drm-intel-nightly changes. v5: - Rebase after the new stolen_lock patch. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: add dev_priv->mm.stolen_lockPaulo Zanoni2-2/+18
Which should protect dev_priv->mm.stolen usage. This will allow us to simplify the relationship between stolen memory, FBC and struct_mutex. v2: - Rebase after the stolen_remove_node() dev_priv patch move. - I realized that after we fixed a few things related to the FBC CFB size checks, we're not reallocating the CFB anymore with FBC enabled, so we can just move all the locking to i915_gem_stolen.c and stop worrying about freezing all the stolen alocations while freeing/rellocating the CFB. This allows us to fix the "Too coarse" observation from Chris. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: move FBC code out of i915_gem_stolen.cPaulo Zanoni5-132/+128
With the abstractions created by the last patch, we can move this code and the only thing inside intel_fbc.c that knows about dev_priv->mm is the code that reads stolen_base. We also had to move a call to i915_gem_stolen_cleanup_compression() - now called intel_fbc_cleanup_cfb() - outside i915_gem_stolen.c. v2: - Rebase after the remove_node() changes on the previous patch. Requested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: add simple wrappers for stolen node insertion/removalPaulo Zanoni2-16/+37
We want to move the FBC code out of i915_gem_stolen.c, but that code directly adds/removes stolen memory nodes. Let's create this abstraction, so i915_gme_stolen.c is still in control of all the stolen memory handling. The abstraction will also allow us to add locking assertions later. v2: - Add dev_priv as remove_node() argument since we'll need it later (Chris). Requested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Drop a spurious intel_pre_plane_update() callVille Syrjälä1-2/+0
Kill the extra intel_pre_plane_update() I accidentally added in commit 852eb00dc44ea2b8896e2fa27c6a36a1f697ba5a Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Jun 24 22:00:07 2015 +0300 drm/i915: Try to make sure cxsr is disabled around plane enable/disable This fixes a load of warnings from the frontbuffer tracking. Testcase: igt/kms_frontbuffer_tracking/fbc-1p-rte Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/opregion: start using extended didlJani Nikula1-7/+21
Adding support for did2, or the extended support display devices ID list, increases the total to 15. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/opregion: abstract didl and did2 getter and setterJani Nikula1-11/+39
Make it easier to handle the extended didl. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/opregion: prefer DRM logging functions over pr_warn and dev_dbgJani Nikula1-7/+3
Conform to same style as the rest of the driver. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/opregion: add new opregion stuffJani Nikula1-3/+12
Inluding extended didl and cpdl fields Present since opregion version 3.0. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizesJani Nikula1-0/+5
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/hotplug: document the hotplug handling in the driverJani Nikula1-0/+39
Add an overview of the drm/i915 hotplug handling. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/audio: clarify HD audio documentation wrt modesetJani Nikula1-1/+2
Clarify that audio enable/disable sequences are part of the modeset sequence. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: set FDI translations to NULL on SKLPaulo Zanoni1-0/+1
drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’: drivers/gpu/drm/i915/intel_ddi.c:517:6: warning: ‘ddi_translations_fdi’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (ddi_translations_fdi) ^ drivers/gpu/drm/i915/intel_ddi.c:446:30: note: ‘ddi_translations_fdi’ was declared here const struct ddi_buf_trans *ddi_translations_fdi; ^ This line used to be there, but was removed by: commit f8896f5d58e64bfd3c2b5f7c5ba5c3f3967e93c7 Author: David Weinehall <david.weinehall@linux.intel.com> Date: Thu Jun 25 11:11:03 2015 +030 drm/i915/skl: Buffer translation improvements Cc: David Weinehall <david.weinehall@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/chv: fix HW readout of the port PLL fractional dividerImre Deak1-2/+5
Ville noticed that the PLL HW readout code parsed the fractional divider value as if the fractional divider was always enabled. This may result in a port clock state check mismatch if the preceeding modeset disabled the fractional divider, but left a non-zero divider value in the register. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag and getparamAbdiel Janulgue3-0/+20
Ensures that the batch buffer is executed by the resource streamer. And will let userspace know whether Resource Streamer is supported in the kernel. v2: Don't skip 1<<15 for the exec flags (Jani Nikula) v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson) (from getparam patch) v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after I915_PARAM_HAS_GPU_RESET. v3: Only advertise RS support for hardware that supports it. v4: Add HAS_RESOURCE_STREAMER() macro (Chris) Testcase: igt/gem_exec_params Cc: Jani Nikula <jani.nikula@intel.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [danvet: squash in getparam patch since it'd break bisect, suggested by Chris.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Enable resource streamer on ExeclistsAbdiel Janulgue2-2/+7
GEN8 and above uses Execlists by default instead of the legacy ringbuffer for batch execution. This patch enables the resource streamer bits when required. Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com> This version also adds the required bits to enable GEN8 Resource Streamer context save and restore for Execlists. Cc: ville.syrjala@linux.intel.com Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Enable Resource Streamer state save/restore on MI_SET_CONTEXTAbdiel Janulgue2-2/+7
Also clarify comments on context size that the extra state for Resource Streamer is included. v2: Don't remove the extended save/restore enabled for older platforms. (Ville) Use new MI_SET_CONTEXT defines for HSW RS save/restore state instead of extended save/restore. (Daniel) Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_STARTAbdiel Janulgue3-2/+8
Adds support for enabling the resource streamer on the legacy ringbuffer for HSW and GEN8. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915/bxt: BUNs related to port PLLVandana Kannan3-11/+7
This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment v3: Move DCO amplitude default value to i915_reg.h. Suggested by Siva. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2] [danvet: Spell out BUN since not everyone knows what this means.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06Revert "drm/i915: Disable 12bpc hdmi for now"Ville Syrjälä1-2/+1
HDMI 12bpc should be working fine now. Let it loose. This reverts commit 5e3daaca09f5158eff9c92290faa1d2001ecc6e4. v2: Rebased due to CHV/BXT port clock check improvemnts Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Account for CHV/BXT DPLL clock limitationsVille Syrjälä1-15/+43
CHV/BXT DPLL can't generate frequencies in the 216-240 MHz range. Account for that when checking whether the HDMI port clock is valid. This is particularly important for BXT since it can otherwise do 12bpc, and standard 1920x1080p60 CEA modes land right in the middle of that range when the clock gets multiplied to account for 12bpc. With the extra checks we will now filter out any mode where both 8bpc and 12bpc clock are within the gap. During modeset we then pick whichever mode works, favoring 12bpc if both are possible. 12bpc isn't supported on CHV so we simply end up filtering out any mode where the 8bpc port clock is in the gap. v2: Fix crtc_clock vs. port_clock fumble in compute_config() (Imre) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Bump HDMI min port clock to 25 MHzVille Syrjälä1-1/+1
Increase the HDMI port minimum port clock from 20 to 25 MHz. This is is the minimum listed in the DVI/HDMI specs, and it's also the documented minimum DPLL frequency for most of our platforms. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-06drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä1-25/+24
Take the HDMI 12bpc mode and pixel repeat into account when extracting the dotclock from the hardware on DDI platforms. Tested on HSW only. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: Update DRIVER_DATE to 20150703Daniel Vetter1-1/+1
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915/gtt: Per ppgtt scratch pageMika Kuoppala1-20/+74
Previously we have pointed the page where the individual ppgtt scratch structures refer to, to be the instance which GGTT setup have allocated. So it has been shared. To achieve full isolation between ppgtts also in this regard, allocate per ppgtt scratch page. Cc: Michel Thierry <michel.thierry@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh1-6/+20
On CHT, changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. v2 by Jani, rebased on earlier refactoring, original at [1]. [1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: Support for higher DSI clkGaurav K Singh1-2/+2
For MIPI panels requiring higher DSI clk, values needs to be added in lfsr_converts table for getting the correct values of pll ctrl and dividor values which gets programmed in cck regs, otherwise DSI PLL does not get locked leading to no display on the MIPI panel. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula1-43/+24
Nuke three copies of the same switch case. Hopefully we can switch to a drm generic function later on, but that will require us to swich to enum mipi_dsi_pixel_format first. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: don't increment the FBC threshold at fbc_enablePaulo Zanoni1-4/+6
We first set the threshold value when we're allocating the CFB, and then later at {ilk,gen7}_fbc_enable() we increment it in case we're using 16bpp. While that is correct, it is dangerous: if we rework the code a little bit in a way that allows us to call intel_fbc_enable() without necessarily calling i915_gem_stolen_setup_compression() first, we might end up incrementing threshold more than once. To prevent that, increment a temporary variable instead. v2: Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: Report correct GGTT space usageTvrtko Ursulin2-9/+26
Currently only normal views were accounted which under-accounts the usage as reported in debugfs. Introduce new helper, i915_gem_obj_total_ggtt_size, and use it from call sites which want to know how much GGTT space are objects using. v2: Single loop in i915_gem_get_aperture_ioctl. (Chris Wilson) v3: Walk GGTT active/inactive lists in i915_gem_get_aperture_ioctl for better efficiency. (Chris Wilson, Daniel Vetter) v4: Make i915_gem_obj_total_ggtt_size private to debugfs. (Chris Wilson) v5: Change unsigned long to u64. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915/gtt: Return struct i915_scratch_page from alloc_scratchMika Kuoppala1-41/+37
Every other alloc_* function return the pointer to the page they alloc. Follow the convention with scratch page also. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915/gtt: Reorder page alloc/free/init functionsMika Kuoppala1-83/+83
Maintain base page handling functions in order of alloc, free, init. No functional changes. v2: s/Introduce/Maintain (Michel) v3: Rebase Cc: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915: Reserve space improvementsJohn Harrison3-77/+90
An earlier patch was added to reserve space in the ring buffer for the commands issued during 'add_request()'. The initial version was pessimistic in the way it handled buffer wrapping and would cause premature wraps and thus waste ring space. This patch updates the code to better handle the wrap case. It no longer enforces that the space being asked for and the reserved space are a single contiguous block. Instead, it allows the reserve to be on the far end of a wrap operation. It still guarantees that the space is available so when the wrap occurs, no wait will happen. Thus the wrap cannot fail which is the whole point of the exercise. Also fixed a merge failure with some comments from the original patch. v2: Incorporated suggestion by David Gordon to move the wrap code inside the prepare function and thus allow a single combined wait_for_space() call rather than doing one before the wrap and another after. This also makes the prepare code much simpler and easier to follow. v3: Fix for 'effective_size' vs 'size' during ring buffer remainder calculations (spotted by Tomas Elf). For: VIZ-5115 CC: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak1-0/+20
For the purpose of state checking we only care about the DPLL HW flags that we actually program, so mask off the ones that we don't. This fixes one set of DPLL state check failures. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-03Merge tag 'drm-intel-next-fixes-2015-07-02' of ↵Linus Torvalds6-3/+29
git://anongit.freedesktop.org/drm-intel Pull intel drm fixes from Jani Nikula: "Almost all of it is regression fixes all around, with cc: stable, and then there's Ander's fix for one of the warnings you reported. We're still working on the rest" [ Dave is on vacation, and Jani is heading out on vacation too ] * tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm-intel: drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel() drm/i915: fix backlight after resume on 855gm agp/intel: Fix typo in needs_ilk_vtd_wa() drm/i915/ppgtt: Break loop in gen8_ppgtt_clear_range failure path drm/i915: Fix IPS related flicker
2015-06-30drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()Ander Conselvan de Oliveira1-0/+3
Similarly to what is done for SKL, clear the dpll_hw_state of the pipe config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values. That can happen if a crtc that was previously driving an HDMI connector switches to a DP connector. In that case, the wrpll field was left with its old value, leading to warnings like the one below: [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000) ------------[ cut here ]------------ WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]() pipe state doesn't match! This regression was indroduced in commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Fri May 15 13:34:29 2015 +0300 drm/i915: Don't overwrite (e)DP PLL selection on SKL Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Tested-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-30drm/i915/bxt: add DDI port HW readout supportImre Deak2-8/+29
Add support for reading out the HW state for DDI ports. Since the actual programming is very similar to the CHV/VLV DPIO PLL programming we can reuse much of the logic from there. This fixes the state checker failures I saw on my BXT with HDMI output. v2: - rebased on v2 of patch 4/5 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-30drm/i915: calculate the port clock rate along with other PLL paramsImre Deak2-25/+38
Depending on the platform the port clock fed to the pipe can be the PLL's post-divided fast clock rate or a /5 divided version of it. To make this more obvious across the platforms calculate this port clock along with the rest of the PLL parameters. This is also needed by the next patch where we can reuse the CHV helper for the BXT PLL HW readout code; so export the corresponding helper. While at it also add a more descriptive name to the helpers and a comment explaining what's being calculated. No functional change. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-30drm/i915/vlv: move the vlv PLL helper next to its platform counterpartsImre Deak1-10/+10
Move the helper next to the PLL helpers of the other platforms for clarity. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-30drm/i915/bxt: add PLL10 to the PLL state dumperImre Deak1-1/+2
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-30drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak4-7/+21
Although we have a fixed setting for the PLL9 and EBB4 registers, it still makes sense to check them together with the rest of PLL registers. While at it also remove a redundant comment about 10 bit clock enabling. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-30drm/i915/skl: Buffer translation improvementsDavid Weinehall5-213/+423
This patch adds support for 0.85V VccIO on Skylake Y, separate buffer translation tables for Skylake U, and support for I_boost for the entries that needs this. Changes in v2: * Refactored the code a bit to move all DDI signal level setup to intel_ddi.c Issue: VIZ-5677 Signed-off-by: David Weinehall <david.weinehall@linux.intel.com> Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com> [danvet: Apply style polish checkpatch suggested.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: fix backlight after resume on 855gmJani Nikula2-0/+9
Some 855gm models (at least ThinkPad X40) regressed because of commit b0cd324faed23d10d66ba6ade66579c681feef6f Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Nov 12 16:25:43 2014 +0200 drm/i915: don't save/restore backlight hist ctl registers which tried to make our driver more robust by not blindly saving and restoring registers, but it failed to take into account commit 0eb96d6ed38430b72897adde58f5477a6b71757a Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Oct 14 12:33:41 2009 -0700 drm/i915: save/restore BLC histogram control reg across suspend/resume Fix the regression by enabling hist ctl on gen2. v2: Improved the comment. v3: Improved the comment, again. Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net> References: http://mid.gmane.org/20150623222648.GD12335@acheron Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-29drm/i915: Zero unused WM1 watermarks on VLV/CHVVille Syrjälä1-0/+6
The hardware supposedly ignores the WM1 watermarks while the PND deadline mode is enabled, but clear out the register just in case. This is what the other OS does, and it does make register dumps look more consistent when we don't have partial WM1 values lingering in the registers (some WM1 watermarks already get zeroed when the actually used DSPFW registers get written). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: Add debugfs knobs for VLVCHV memory latency valuesVille Syrjälä1-5/+19
Allow tweaking the VLV/CHV memory latencies thorugh sysfs, like we do for ILK+. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: Don't do PM5/DDR DVFS with multiple pipesVille Syrjälä1-0/+3
Enabling PM5/DDR DVFS with multiple active pipes isn't a validated configuration. It does seem to work most of the time at least, but there is clearly an additional risk of underruns, so let's not play with fire. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: Try to make sure cxsr is disabled around plane enable/disableVille Syrjälä3-12/+38
CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control register (enable bit at least, not quite sure about the rest). So in order to have the plane enable/disable when we want we need to first kick the hardware out of cxsr. Unfortunateloy this requires some extra vblank waits. For the CxSR enable after the plane update we should eventually use an async vblank worker, but since we don't have that just do sync vblank waits. For the disable case we have no choice but to do it synchronously. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: Use the memory latency based WM computation on VLV tooVille Syrjälä3-225/+6
In order to get decnet memory self refresh residency on VLV, flip it over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS so it's a bit simpler. I'm not sure the currently memory latency used for CHV is really appropriate for VLV. Some further testing will probably be needed to figure that out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-29drm/i915: Compute display FIFO split dynamically for CHVVille Syrjälä2-11/+189
Consider which planes are active and compute the FIFO split based on the relative data rates. Since we only consider the pipe src width rather than the plane width when computing watermarks it seems best to do the same when computing the FIFO split as well. This means the only thing we actually have to consider for the FIFO splut is the bpp, and we can ignore the rest. I've just stuffed the logic into the watermark code for now. Eventually it'll need to move into the atomic update for the crtc. There's also one extra complication I've not yet considered; Some of the DSPARB registers contain bits related to multiple pipes. The registers are double buffered but apparently they update on the vblank of any active pipe. So doing the FIFO reconfiguration properly when multiple pipes are active is not going to be fun. But let's ignore that mess for now. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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