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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)AuthorFilesLines
2021-02-09drm/i915: Disable atomics in L3 for gen9Chris Wilson2-0/+15
2021-02-09drm/i915/gem: Move freeze/freeze_late next to suspend/suspend_lateChris Wilson6-43/+46
2021-02-09drm/i915/gem: Fix oops in error handling codeDan Carpenter1-8/+4
2021-02-09drm/i915/gvt: fix uninitialized return in intel_gvt_update_reg_whitelist()Dan Carpenter1-1/+2
2021-02-09drm/i915: Restrict DRM_I915_DEBUG to developer buildsChris Wilson1-0/+2
2021-02-08i915: kvmgt: the KVM mmu_lock is now an rwlockPaolo Bonzini1-6/+6
2021-02-04Merge tag 'drm-intel-next-2021-01-29' of git://anongit.freedesktop.org/drm/dr...Dave Airlie14-241/+415
2021-02-02drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent modeImre Deak3-10/+14
2021-02-02drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.cImre Deak4-21/+20
2021-02-02drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
2021-02-02drm/i915/gem: Drop lru bumping on display unpinningChris Wilson4-53/+4
2021-02-02drm/i915/gt: Close race between enable_breadcrumbs and cancel_breadcrumbsChris Wilson1-2/+4
2021-02-02drm/i915/gt: Move the breadcrumb to the signaler if completed upon cancelChris Wilson1-19/+22
2021-02-02drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
2021-02-02drm/i915: Power up combo PHY lanes for for HDMI as wellVille Syrjälä1-0/+2
2021-02-02drm/i915: Extract intel_ddi_power_up_lanes()Ville Syrjälä1-16/+19
2021-02-02drm/i915: Skip vswing programming for TBTVille Syrjälä1-0/+6
2021-01-29drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak1-21/+15
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä4-6/+52
2021-01-29drm/i915: Implement async flip for ilk/snbVille Syrjälä3-1/+31
2021-01-29drm/i915: Implement async flip for ivb/hswVille Syrjälä3-1/+32
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä4-14/+73
2021-01-29drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä3-16/+83
2021-01-29drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_neededJosé Roberto de Souza3-10/+9
2021-01-29drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza4-75/+93
2021-01-29drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza3-42/+12
2021-01-29Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/dr...Dave Airlie49-5411/+6845
2021-01-28drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
2021-01-28drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul1-11/+1
2021-01-28drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
2021-01-28drm/i915: WARN if plane src coords are too bigVille Syrjälä2-0/+11
2021-01-27drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare1-1/+1
2021-01-26drm/i915/gt: Always try to reserve GGTT address 0x0Chris Wilson1-12/+35
2021-01-26drm/i915: Always flush the active worker before returning from the waitChris Wilson1-13/+15
2021-01-26drm/i915/selftest: Fix potential memory leakPan Bian1-1/+1
2021-01-26drm/i915: Check for all subplatform bitsUmesh Nerlige Ramappa1-1/+1
2021-01-26drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-26drm/i915/gt: Clear CACHE_MODE prior to clearing residualsChris Wilson1-0/+12
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä2-6/+48
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä5-271/+140
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä1-55/+88
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä2-11/+12
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä1-37/+18
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2-16/+21
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
2021-01-26drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
2021-01-26drm/i915: Fix vblank timestamps with VRRVille Syrjälä4-6/+34
2021-01-26drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
2021-01-26drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-16 21:10:38 +0300