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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
AgeCommit message (Expand)AuthorFilesLines
2015-08-05drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau1-5/+10
2015-08-05drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau1-5/+10
2015-07-13drm/i915: Refactor VLV display power well init/deinitVille Syrjälä1-29/+23
2015-07-13drm/i915: Simplify CHV pipe A power well codeVille Syrjälä1-27/+20
2015-07-13drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä1-4/+4
2015-07-13drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä1-4/+4
2015-05-28drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä1-94/+4
2015-05-28drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä1-0/+2
2015-05-20drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida1-2/+2
2015-05-08Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä1-12/+2
2015-05-08drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä1-5/+31
2015-05-08drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau1-0/+1
2015-05-08drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau1-1/+2
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah1-4/+36
2015-05-08Implement enable/disable for Display C6 stateA.Sunil Kamath1-2/+25
2015-05-08drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah1-7/+36
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah1-5/+46
2015-05-08drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath1-2/+39
2015-05-08drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah1-0/+33
2015-04-16drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath1-0/+66
2015-04-14drm/i915/bxt: Define BXT power domainsSatheeshakrishna M1-0/+55
2015-03-18drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven1-3/+3
2015-03-18drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau1-1/+3
2015-03-18drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau1-1/+1
2015-03-18drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau1-0/+31
2015-03-18drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau1-1/+1
2015-03-18drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau1-4/+6
2015-03-18drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau1-1/+2
2015-02-14drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M1-0/+220
2015-01-27drm/i915/skl: Adding power domains for AUX controllersSatheeshakrishna M1-0/+15
2015-01-13Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter1-83/+0
2015-01-12drm/i915: remove unused power_well/get_cdclk_freq apiImre Deak1-56/+0
2014-12-18drm/i915: Kill check_power_well() callsVille Syrjälä1-27/+0
2014-12-16drm/i915: tame the chattermouth (v2)Rob Clark1-1/+1
2014-12-03drm/i915: Fix short description of intel_display_power_is_enabled()Damien Lespiau1-1/+1
2014-11-17drm/i915: Reinit display irqs and hpd from chv pipe-a power wellVille Syrjälä1-0/+23
2014-11-05drm/i915: Enable pipe-a power well on chvVille Syrjälä1-1/+12
2014-11-05drm/i915: Do vlv cmnlane toggle w/a in more casesVille Syrjälä1-5/+2
2014-10-24drm/i915: only run hsw_power_well_post_enable when really neededPaulo Zanoni1-1/+1
2014-10-03drm/i915: Use dev_priv instead of dev in irq setup functionsDaniel Vetter1-1/+1
2014-10-01drm/i915: Kerneldoc for intel_runtime_pm.cDaniel Vetter1-1/+165
2014-10-01drm/i915: Call runtime_pm_disable directlyDaniel Vetter1-16/+18
2014-10-01drm/i915: Move intel_display_set_init_power to intel_runtime_pm.cDaniel Vetter1-0/+14
2014-10-01drm/i915: Bikeshed rpm functions name a bit.Daniel Vetter1-8/+13
2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter1-0/+1190
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