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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-21drm/i915: Pre-calculate plane relative data rateVille Syrjälä1-151/+36
2022-03-21drm/i915: Tweak plane ddb allocation trackingVille Syrjälä1-63/+45
2022-03-21drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä1-4/+6
2022-03-18drm/i915: Rename pre-icl SAGV enable/disable functionsVille Syrjälä1-18/+14
2022-03-18drm/i915: Reject excessive SAGV block timeVille Syrjälä1-0/+6
2022-03-18drm/i915: Probe whether SAGV works on pre-iclVille Syrjälä1-0/+14
2022-03-18drm/i915: Rework SAGV block time probingVille Syrjälä1-15/+21
2022-03-18drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä1-4/+6
2022-03-09drm/i915: Remove leftover cnl SAGV block timeVille Syrjälä1-3/+0
2022-03-08drm/i915: Don't skip ddb allocation if data_rate==0Ville Syrjälä1-18/+12
2022-03-03drm/i915: Don't skip ddb allocation if data_rate==0Ville Syrjälä1-18/+12
2022-03-02drm/i915: Use str_enabled_disabled()Lucas De Marchi1-2/+2
2022-03-02drm/i915: Use str_yes_no()Lucas De Marchi1-4/+6
2022-02-28drm/i915/wm: use REG_FIELD_{PREP,GET} for PLANE_WM_BLOCKS_MASKJani Nikula1-2/+2
2022-02-24drm/i915/dg2: Tile 4 plane format supportStanislav Lisovskiy1-0/+1
2022-02-18drm/i915: Pimp icl+ sagv pre/post updateVille Syrjälä1-18/+17
2022-02-18drm/i915: Split pre-icl vs. icl+ SAGV hooks apartVille Syrjälä1-40/+74
2022-02-18drm/i915: Correctly populate use_sagv_wm for all pipesVille Syrjälä1-11/+11
2022-02-18drm/i915: Polish ilk+ wm register bitsVille Syrjälä1-29/+28
2022-02-18drm/i915: Clean up SSKPD/MLTR definesVille Syrjälä1-13/+13
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper1-0/+1
2022-02-16drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update()Ville Syrjälä1-4/+6
2022-02-16drm/i915: Use {active,scaled}_planes to compute ilk watermarksVille Syrjälä1-6/+2
2022-02-11drm/i915: Extract skl_allocate_plane_ddb()Ville Syrjälä1-17/+24
2022-02-11drm/i915: Introduce skl_plane_ddb_iterVille Syrjälä1-48/+49
2022-02-11drm/i915: Fix plane relative_data_rate calculationVille Syrjälä1-61/+2
2022-02-11drm/i915: Extract skl_ddb_entry_init()Ville Syrjälä1-19/+25
2022-02-11drm/i915: Drop pointless dev_priv argumentVille Syrjälä1-6/+5
2022-02-09drm/i915/pm: hide struct drm_i915_clock_gating_funcsJani Nikula1-0/+4
2022-02-08drm/i915: Fix mbus join config lookupVille Syrjälä1-1/+1
2022-02-08drm/i915: Fix dbuf slice config lookupVille Syrjälä1-1/+1
2022-02-07drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKLVille Syrjälä1-0/+68
2022-02-07drm/i915: Populate pipe dbuf slices more accurately during readoutVille Syrjälä1-5/+8
2022-02-07drm/i915: Allow !join_mbus cases for adlp+ dbuf configurationVille Syrjälä1-20/+46
2022-02-02drm/i915: Move GT registers to their own header fileMatt Roper1-0/+1
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-4/+33
2022-01-26drm/i915: Use single_enabled_crtc() in i9xx_update_wm()Ville Syrjälä1-15/+11
2022-01-26drm/i915: Use the correct plane source width in watermark calculationsVille Syrjälä1-11/+10
2022-01-26drm/i915: Fix up pixel_rate vs. clock confusion in wm calculationsVille Syrjälä1-30/+22
2022-01-26drm/i915: Don't allocate extra ddb during async flip for DG2Stanislav Lisovskiy1-0/+19
2022-01-26drm/i915: Use wm0 only during async flips for DG2Stanislav Lisovskiy1-1/+13
2022-01-26drm/i915: Pass plane to watermark calculation functionsStanislav Lisovskiy1-16/+21
2022-01-24drm/i915: Clean up pre-skl primary plane registersVille Syrjälä1-1/+1
2022-01-19drm/i915: Remove zombie async flip vt-d w/aVille Syrjälä1-12/+0
2022-01-18drm/i915: Use REG_BIT() & co. for universal plane bitsVille Syrjälä1-6/+6
2022-01-13drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*Jani Nikula1-11/+9
2022-01-12drm/i915/gt: Move engine registers to their own headerMatt Roper1-0/+1
2022-01-12drm/i915: Use RING_PSMI_CTL rather than per-engine macrosMatt Roper1-2/+2
2022-01-12drm/i915: Parameterize ECOSKPDMatt Roper1-2/+4
2022-01-08drm/i915: Fix possible NULL pointer dereferences in i9xx_update_wm()Harish Chegondi1-1/+1
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