summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2015-06-04Merge tag 'v4.1-rc6' into drm-nextDave Airlie1-13/+11
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä1-2/+2
2015-05-28drm/i915: Kill intel_flush_primary_plane()Ville Syrjälä1-2/+4
2015-05-26drm/i915: Use spinlocks for checking when to waitboostChris Wilson1-11/+20
2015-05-22drm/i915: Introduce DRM_I915_THROTTLE_JIFFIESChris Wilson1-1/+1
2015-05-22drm/i915: Enable GTT caching on gen8Ville Syrjälä1-0/+13
2015-05-22drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()Ville Syrjälä1-0/+10
2015-05-22drm/i915: Use ilk_init_lp_watermarks() on BDWVille Syrjälä1-3/+1
2015-05-21drm/i915: Free RPS boosts for all laggardsChris Wilson1-4/+16
2015-05-21drm/i915: Convert RPS tracking to a intel_rps_client structChris Wilson1-7/+7
2015-05-21drm/i915: Limit mmio flip RPS boostsChris Wilson1-0/+1
2015-05-21drm/i915: Limit ring synchronisation (sw sempahores) RPS boostsChris Wilson1-0/+1
2015-05-21drm/i915: s/\<rq\>/req/gDaniel Vetter1-8/+8
2015-05-20drm/i915/chv: Set min freq to efficient frequency on chvDeepak S1-19/+2
2015-05-20drm/i915/chv: Extend set idle rps wa to chvDeepak S1-7/+0
2015-05-20drm/i915/vlv: Remove wait for for punit to updates freq.Deepak S1-30/+11
2015-05-20drm/i915: Be optimistic about future display engines having 7 WM levelsDamien Lespiau1-1/+1
2015-05-20drm/i915: Adding dbuf support for skl nv12 format.Chandra Konduru1-12/+67
2015-05-19drm/i915: fix screen flickeringThomas Gummerer1-13/+11
2015-05-08drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau1-2/+1
2015-05-08drm/i915: s/9/intel_freq_opcode(450)/Ville Syrjälä1-2/+2
2015-05-08drm/i915: Setup static bias for GPUDeepak S1-0/+12
2015-04-16drm/i915: Re-adjusting rc6 promotional timer for chvDeepak S1-2/+2
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter1-2/+31
2015-04-14drm/i915/bxt: add workaround to avoid PTE corruptionRobert Beckett1-0/+2
2015-04-14drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaroundBen Widawsky1-1/+3
2015-04-14drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaroundImre Deak1-0/+11
2015-04-14drm/i915/bxt: add bxt_init_clock_gatingImre Deak1-1/+11
2015-04-13drm/i915: Disable Render power gatingSagar Kamble1-2/+5
2015-04-10drm/i915: Naming constants to be written to GEN9_PG_ENABLESagar Kamble1-1/+3
2015-04-10drm/i915: Deminish contribution of wait-boosting from clientsChris Wilson1-3/+15
2015-04-10drm/i915: Boost GPU frequency if we detect outstanding pageflipsChris Wilson1-0/+35
2015-04-10drm/i915: Agressive downclocking on BaytrailChris Wilson1-1/+7
2015-04-10drm/i915/skl: Implement WaDisableVFUnitClockGatingDamien Lespiau1-0/+4
2015-04-10drm/i915/skl: Fix stepping check for a couple of W/AsDamien Lespiau1-1/+1
2015-04-10drm/i915: Silence a sparse warningVille Syrjälä1-1/+1
2015-04-09drm/i915/bxt: Broxton DDB is 512 blocksDamien Lespiau1-1/+5
2015-03-31drm/i915: Convert the ddi cdclk code to get_display_clock_speedVille Syrjälä1-1/+1
2015-03-26drm/i915/skl: fix semicolon.cocci warningskbuild test robot1-1/+1
2015-03-23drm/i915/skl: Take 90/270 rotation into account in watermark calculationsTvrtko Ursulin1-1/+17
2015-03-20drm/i915: Use down ei for manual Baytrail RPS calculationsChris Wilson1-3/+2
2015-03-20drm/i915: Improved w/a for rps on BaytrailChris Wilson1-2/+20
2015-03-20drm/i915: Relax RPS contraints to allows setting minfreq on idleChris Wilson1-16/+28
2015-03-18drm/i915/skl: Enable the RPS interrupts programmingAkash Goel1-14/+3
2015-03-18drm/i915/skl: Updated the gen9_enable_rps functionAkash Goel1-15/+13
2015-03-18drm/i915/skl: Updated the gen6_rps_limits functionAkash Goel1-5/+11
2015-03-18drm/i915/skl: Restructured the gen6_set_rps_thresholds functionAkash Goel1-36/+32
2015-03-18drm/i915/skl: Updated the gen6_set_rps functionAkash Goel1-1/+4
2015-03-18drm/i915/skl: Updated the gen6_init_rps_frequencies functionAkash Goel1-0/+7
2015-03-18drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()Akash Goel1-2/+6