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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2013-09-24Merge tag 'v3.12-rc2' into drm-intel-nextDaniel Vetter1-3/+3
2013-09-21drm/i915: Add POWER_DOMAIN_VGAVille Syrjälä1-0/+3
2013-09-21drm/i915: Refactor power well refcount inc/dec operationsVille Syrjälä1-18/+21
2013-09-21drm/i915: Add intel_display_power_{get, put} to request power for specific do...Ville Syrjälä1-0/+63
2013-09-21drm/i915: Change i915_request power well handlingVille Syrjälä1-9/+34
2013-09-20drm/i915/vlv: honor i915_enable_rc6 boot param on VLVJesse Barnes1-3/+4
2013-09-17drm/i915: Add explicit pipe src size to pipe configVille Syrjälä1-18/+15
2013-09-17drm/i915: Make intel_crtc_active() available outside intel_pm.cVille Syrjälä1-11/+0
2013-09-17drm/i915: Check the clock from adjusted mode in intel_crtc_active()Ville Syrjälä1-1/+4
2013-09-17drm/i915: Use adjusted_mode appropriately when computing watermarksVille Syrjälä1-22/+33
2013-09-17drm/i915: Use adjusted_mode in intel_update_fbc()Ville Syrjälä1-4/+8
2013-09-10drm/i915: Refactor max WM levelVille Syrjälä1-8/+11
2013-09-10drm/i915: Use ilk_compute_wm_level to compute WM_PIPE valuesVille Syrjälä1-23/+21
2013-09-10drm/i915: Constify some watermark dataVille Syrjälä1-10/+10
2013-09-10drm/i915: Pass crtc to intel_update_watermarks()Ville Syrjälä1-14/+24
2013-09-08drm/i915: Track pfit enable state separately from sizeChris Wilson1-3/+3
2013-09-03drm/i915: enable trickle feed on HaswellPaulo Zanoni1-2/+0
2013-09-03drm/i915: Don't mask EI UP interrupt on IVB|SNBMika Kuoppala1-1/+11
2013-09-02Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux int...Dave Airlie1-0/+18
2013-08-23drm/i915: allow package C8+ states on Haswell (disabled)Paulo Zanoni1-1/+12
2013-08-23drm/i915: drop WaMbcDriverBootEnable workaroundJesse Barnes1-17/+0
2013-08-23drm/i915: wrap GEN6_PMIMR changesPaulo Zanoni1-1/+1
2013-08-22drm/i915: Only unmask required PM interruptsVinit Azad1-2/+2
2013-08-22drm/i915: clarify Haswell power well bit namesPaulo Zanoni1-6/+7
2013-08-22drm/i915: tune the RC6 threshold for stabilityStéphane Marchesin1-1/+4
2013-08-09drm/i915: Fix FB WM for HSWVille Syrjälä1-1/+2
2013-08-09drm/i915: fix a limit check in hsw_compute_wm_results()Dan Carpenter1-1/+1
2013-08-08drm/i915: Pass plane and crtc to intel_update_sprite_watermarksVille Syrjälä1-18/+16
2013-08-08drm/i915: Split plane watermark parameters into a separate structVille Syrjälä1-30/+27
2013-08-08drm/i915: Pull some watermarks state into a separate structureVille Syrjälä1-23/+25
2013-08-08drm/i915: Calculate max watermark levels for ILK+Ville Syrjälä1-12/+107
2013-08-08drm/i915: Rename hsw_lp_wm_result to intel_wm_levelVille Syrjälä1-14/+6
2013-08-08drm/i915: Pull watermark level validity check outVille Syrjälä1-7/+44
2013-08-08drm/i915: Rename hsw_data_buf_partitioning to intel_ddb_partitioningVille Syrjälä1-11/+6
2013-08-08drm/i915: Kill fbc_enable from hsw_lp_wm_resultsVille Syrjälä1-10/+2
2013-08-08drm/i915: Split watermark level computation from the codeVille Syrjälä1-17/+34
2013-08-08drm/i915: Use 'enabled' instead of 'enable' consistently in sprite WM codeVille Syrjälä1-4/+4
2013-08-07drm/i915: update last_vblank when disabling the power wellPaulo Zanoni1-0/+18
2013-08-05drm/i915: Add comments about units of latency valuesVille Syrjälä1-3/+14
2013-08-05drm/i915: Use the watermark latency values from dev_priv for ILK/SNB/IVB tooVille Syrjälä1-30/+27
2013-08-05drm/i915: Disable specific watermark levels when latency is zeroVille Syrjälä1-0/+6
2013-08-05drm/i915: Print the watermark latencies during initVille Syrjälä1-0/+37
2013-08-05drm/i915: Use the stored cursor and plane latencies properlyVille Syrjälä1-15/+21
2013-08-05drm/i915: Store the watermark latency values in dev_privVille Syrjälä1-9/+53
2013-08-05drm/i915: Add ILK support to intel_read_wm_latencyVille Syrjälä1-0/+7
2013-08-05drm/i915: Add VM to pinBen Widawsky1-1/+1
2013-08-05drm/i915: Add SNB/IVB support to intel_read_wm_latencyVille Syrjälä1-0/+7
2013-08-05drm/i915: Don't multiply the watermark latency values too earlyVille Syrjälä1-5/+5
2013-08-05drm/i915: Split out reading of HSW watermark latency valuesVille Syrjälä1-14/+20
2013-08-05drm/i915: Change the watermark latency type to uint16_tVille Syrjälä1-3/+3
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