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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2014-03-18Merge tag 'v3.14-rc7' into drm-nextDave Airlie1-2/+4
2014-03-08drm/i915: Avoid div by zero when pixel clock is largeVille Syrjälä1-4/+4
2014-03-08drm/i915: power domains: add vlv power wellsImre Deak1-0/+236
2014-03-08drm/i915: sanity check power well sw state against hw stateImre Deak1-3/+35
2014-03-08drm/i915: factor out reset_vblank_counterImre Deak1-1/+8
2014-03-08drm/i915: add port power domainsImre Deak1-0/+9
2014-03-08drm/i915: add noop power well handlers instead of NULL checking themImre Deak1-8/+21
2014-03-08drm/i915: split power well 'set' handler to separate enable/disable/sync_hwImre Deak1-24/+49
2014-03-08drm/i915: add init power domain to always-on power wellsImre Deak1-1/+2
2014-03-08drm/i915: move power domain macros to intel_pm.cImre Deak1-2/+18
2014-03-08drm/i915: fold in __intel_power_well_get/put functionsImre Deak1-24/+13
2014-03-06drm/i915: Unify CHICKEN_PIPESL_1 register definitionsVille Syrjälä1-4/+4
2014-03-06drm/i915: Use RMW to update chicken bits in gen7_enable_fbc()Ville Syrjälä1-2/+5
2014-03-06drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDWVille Syrjälä1-2/+2
2014-03-06drm/i915: Replace a few for_each_pipe(i) by for_each_pipe(pipe)Damien Lespiau1-8/+8
2014-03-06drm/i915: Implement WaDisableSDEUnitClockGating:bdwVille Syrjälä1-0/+4
2014-03-06drm/i915: Disable semaphore wait event idle message on BDWVille Syrjälä1-0/+3
2014-03-06drm/i915: Add thread stall DOP clock gating workaround on Broadwell.Kenneth Graunke1-0/+5
2014-03-06drm/i915: Add a partial instruction shootdown workaround on Broadwell.Kenneth Graunke1-0/+4
2014-03-06drm/i915: kill dev_priv->pc8.gpu_idlePaulo Zanoni1-2/+1
2014-03-06drm/i915/bdw: Add FBC supportBen Widawsky1-1/+1
2014-03-06drm/i915: move hsw power domain comment to its right placeImre Deak1-6/+6
2014-03-06drm/i915: use drm_i915_private everywhere in the power domain apiImre Deak1-40/+25
2014-03-06Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"Chris Wilson1-3/+5
2014-03-06drm/i915: Revert workaround for disabling L3 cache aging on BYTSinclair Yeh1-3/+0
2014-03-04drm/i915: Add a comment about WIZ hashing vs. thread countsVille Syrjälä1-0/+16
2014-03-04drm/i915: Change BDW WIZ hashing mode to 16x4Ville Syrjälä1-0/+7
2014-03-04drm/i915: Change HSW WIZ hashing mode to 16x4Ville Syrjälä1-0/+7
2014-03-04drm/i915: Change IVB WIZ hashing mode to 16x4Ville Syrjälä1-0/+7
2014-03-04drm/i915: There's no need to mask all 3D_CHICKEN bits on SNBVille Syrjälä1-3/+2
2014-03-04drm/i915: Assume we implement WaStripsFansDisableFastClipPerformanceFix:snbVille Syrjälä1-0/+1
2014-03-04drm/i915: Fix SNB GT_MODE register setupVille Syrjälä1-5/+7
2014-03-03drm/i915: vlv: reserve GT power context earlyImre Deak1-2/+4
2014-02-14drm/i915: Don't allocate context pages as mappableDaniel Vetter1-1/+1
2014-02-14drm/i915: Consolidate binding parameters into flagsDaniel Vetter1-1/+1
2014-02-12drm/i915/bdw: Use centralized rc6 info printBen Widawsky1-3/+3
2014-02-12drm/i915: Just print rc6 factsBen Widawsky1-9/+3
2014-02-12drm/i915: Stop pretending VLV has rc6+Ben Widawsky1-3/+3
2014-02-12drm/i915: Clarify RC6 enablingBen Widawsky1-7/+3
2014-02-12drm/i915: Always use INTEL_INFO() to access the device_info structureDamien Lespiau1-4/+9
2014-02-12drm/i915: Disable SF pipelined attribute fetch for SNBVille Syrjälä1-0/+8
2014-02-07drm/i915: Update rps interrupt limitsJeff McGee1-1/+10
2014-02-07drm/i915: Restore rps/rc6 on resetJeff McGee1-11/+24
2014-02-04drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power...Deepak S1-1/+54
2014-02-04drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2Ville Syrjälä1-7/+0
2014-02-04drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnableVille Syrjälä1-3/+10
2014-01-30drm/i915: enable HiZ Raw Stall Optimization on IVBChia-I Wu1-0/+4
2014-01-30drm/i915: enable HiZ Raw Stall Optimization on HSWChia-I Wu1-0/+4
2014-01-29drm/i915: Disable/Enable PM Intrrupts based on the current freq.Deepak S1-0/+3
2014-01-29Revert "drm/i915: set conservative clock gating values on VLV v2"Ville Syrjälä1-10/+1
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