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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2015-12-08drm/i915/skl: Double RC6 WRL always onMika Kuoppala1-2/+1
2015-12-08drm/i915/skl: Disable coarse power gating up until F0Mika Kuoppala1-1/+1
2015-11-18drm/i915: Fix gpu frequency change tracingMika Kuoppala1-1/+1
2015-11-16drm/i915: Fix GT frequency roundingMika Kuoppala1-3/+5
2015-11-02drm/i915/skl: Prevent unclaimed register writes on skylake.Maarten Lankhorst1-0/+5
2015-10-27drm/i915: Fix maxfifo watermark calc on vlv cursor planesThomas Daniel1-1/+1
2015-10-13drm/i915: Move skl/bxt gt specific workarounds to ring initMika Kuoppala1-60/+0
2015-10-13drm/i915: revert a few more watermark commitsPaulo Zanoni1-163/+256
2015-10-09drm/i915: Partial revert of atomic watermark seriesMatt Roper1-103/+129
2015-10-07drm/i915/chv: remove pre-production hardware workaroundsJani Nikula1-34/+22
2015-10-06drm/i915: Update Promotion timer for RC6 TO ModeSagar Arun Kamble1-4/+6
2015-09-30drm/i915: Calculate watermark configuration during atomic check (v2)Matt Roper1-52/+12
2015-09-30drm/i915: Calculate ILK-style watermarks during atomic check (v3)Matt Roper1-45/+43
2015-09-30drm/i915: Calculate pipe watermarks into CRTC state (v3)Matt Roper1-17/+27
2015-09-30drm/i915: Refactor ilk_update_wm (v3)Ville Syrjälä1-29/+35
2015-09-30drm/i915: Drop intel_update_sprite_watermarksMatt Roper1-58/+0
2015-09-30drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic checkMatt Roper1-23/+12
2015-09-30drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)Matt Roper1-175/+151
2015-09-30drm/i915/skl: Simplify wm structures slightly (v2)Matt Roper1-45/+48
2015-09-30drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2)Matt Roper1-55/+29
2015-09-30drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)Matt Roper1-63/+70
2015-09-30drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/Ville Syrjälä1-2/+2
2015-09-30drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä1-20/+5
2015-09-30drm/i915/skl: Remove WaDisableVFUnitClockGatingArun Siluvery1-6/+0
2015-09-30drm/i915/skl: Remove WaSetGAPSunitClckGateDisableArun Siluvery1-6/+0
2015-09-30drm/i915/skl: Remove WaDisableSDEUnitClockGatingArun Siluvery1-3/+1
2015-09-30drm/i915/bxt: Add WaStoreMultiplePTEenable nameArun Siluvery1-6/+3
2015-09-30drm/i915: Constify adjusted_modeVille Syrjälä1-6/+3
2015-09-30drm/i915: Always call the adjusted mode 'adjusted_mode'Ville Syrjälä1-8/+6
2015-09-30Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter1-13/+29
2015-09-23drm/i915: Replace raw numbers with the approproate register name in ILK turbo...Ville Syrjälä1-3/+3
2015-09-23drm/i915: Parametrize ILK turbo registersVille Syrjälä1-7/+7
2015-09-23drm/i915: Program GuC MAX IDLE CountSagar Arun Kamble1-0/+4
2015-09-23drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGatingSagar Arun Kamble1-1/+7
2015-09-23drm/i915: WaRsUseTimeoutModeSagar Arun Kamble1-3/+10
2015-09-23drm/i915: WaRsDisableCoarsePowerGatingSagar Arun Kamble1-4/+7
2015-09-23drm/i915/bxt: WaGsvDisableTurboSagar Arun Kamble1-0/+10
2015-09-22drm/i915/skl: Don't clear all watermarks when updating. (v2)Bob Paauwe1-1/+25
2015-09-14drm/i915/bxt: Add WaSetClckGatingDisableMediaArun Siluvery1-0/+6
2015-09-10drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOSVille Syrjälä1-13/+29
2015-09-07drm/i915/bxt: Clean up bxt_init_clock_gatingNick Hoath1-5/+11
2015-09-04drm/i915: use the yesno helper for loggingJani Nikula1-2/+2
2015-09-04drm/i915/skl: Avoid using un-initialized bits_per_pixelKumar, Mahesh1-1/+2
2015-09-02drm/i915: Add HAS_PCH_LPT_LP() macroVille Syrjälä1-2/+2
2015-08-06Merge tag 'topic/drm-misc-2015-07-28' into drm-intel-next-queuedDaniel Vetter1-1/+1
2015-08-05drm/i915:skl: Add WaEnableGapsTsvCreditFixArun Siluvery1-0/+6
2015-07-22drm: Simplify drm_for_each_legacy_plane argumentsDaniel Vetter1-1/+1
2015-07-20Partially revert "drm/i915: s/mdelay/msleep/" in ilk rps codeDaniel Vetter1-3/+3
2015-07-17drm/i915: Fix divide by zero on watermark updateMika Kuoppala1-1/+3
2015-07-15drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery1-0/+3
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