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path: root/drivers/gpu/drm/i915/intel_drv.h
AgeCommit message (Expand)AuthorFilesLines
2013-04-30drm/i915: move lvds_border_bits to pipe_configDaniel Vetter1-0/+1
2013-04-29drm/i915: implement fdi auto-ditheringDaniel Vetter1-0/+7
2013-04-29drm/i915: split up fdi_set_m_n into computation and hw setupDaniel Vetter1-1/+2
2013-04-29drm/i915: move intel_crtc->fdi_lanes to pipe_configDaniel Vetter1-1/+3
2013-04-26drm/i915: move PCH pfit controls into pipe_configJesse Barnes1-5/+13
2013-04-26drm/i915: factor out GMCH panel fitting code and use for eDP v3Jesse Barnes1-0/+6
2013-04-25drm/i915: use pipe_config for lvds ditheringDaniel Vetter1-0/+5
2013-04-25drm/i915: keep max backlight internal to intel_panel.cJani Nikula1-2/+2
2013-04-20drm/i915: Make struct dpll == intel_clock_tVille Syrjälä1-5/+13
2013-04-19drm/i915: report Gen5+ CPU and PCH FIFO underrunsPaulo Zanoni1-0/+11
2013-04-19drm/i915: update VLV PLL and DPIO code v11Jesse Barnes1-0/+14
2013-04-19drm/i915/dp: program VSwing and Preemphasis control settings on VLV v2Pallavi G1-0/+2
2013-04-18drm/i915: move cpu_transcoder to the pipe configurationDaniel Vetter1-1/+4
2013-04-18drm/i915: (re)init HPD interrupt storm statisticsEgbert Eich1-0/+4
2013-04-18drm/i915: add intel_using_power_wellPaulo Zanoni1-0/+1
2013-04-03drm/i915: create pipe_config->dpll for clock stateDaniel Vetter1-0/+12
2013-04-03drm/i915: remove leaky eDP functionsDaniel Vetter1-3/+0
2013-04-03drm/i915: track dp target_clock in pipe_configDaniel Vetter1-1/+6
2013-04-03drm/i915: move dp_m_n computation to dp_encoder->compute_configDaniel Vetter1-3/+3
2013-04-03drm/i915: clear up the fdi/dp set_m_n confusionDaniel Vetter1-0/+5
2013-04-02drm/i915: sprite support for ValleyView v4Jesse Barnes1-1/+2
2013-03-28drm/i915: fix up _wait_for macroDaniel Vetter1-2/+11
2013-03-28drm/i915: fold wait_for_atomic_us into wait_for_atomicDaniel Vetter1-13/+2
2013-03-28drm/i915: convert DP autodither code to new infrastructureDaniel Vetter1-3/+0
2013-03-28drm/i915: introduce pipe_config->dither|pipe_bppDaniel Vetter1-1/+3
2013-03-28drm/i915: add pipe_config->limited_color_rangeDaniel Vetter1-5/+7
2013-03-28drm/i915: add pipe_config->has_pch_encoderDaniel Vetter1-6/+7
2013-03-28drm/i915: add pipe_config->pixel_multiplierDaniel Vetter1-16/+3
2013-03-28drm/i915: add pipe_config->timings_setDaniel Vetter1-4/+6
2013-03-28drm/i915: introduce struct intel_crtc_configDaniel Vetter1-0/+7
2013-03-27DRM/I915: Add enum hpd_pin to intel_encoder.Egbert Eich1-0/+1
2013-03-27drm/i915: add sprite restore function v3Jesse Barnes1-0/+5
2013-03-23drm/i915: Rename intel_ddi_enable_pipe_func() to transcoder_func()Damien Lespiau1-1/+1
2013-03-19Merge tag 'v3.9-rc3' into drm-intel-next-queuedDaniel Vetter1-4/+4
2013-02-24Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-in...Dave Airlie1-3/+4
2013-02-22drm/i915: Handle untiled planes when computing their offsetsChris Wilson1-3/+4
2013-02-20Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-in...Dave Airlie1-0/+4
2013-02-20drm/i915: rename sdvox_reg to hdmi_reg on HDMI contextPaulo Zanoni1-2/+2
2013-02-20drm/i915: add aux_ch_ctl_reg to struct intel_dpPaulo Zanoni1-0/+1
2013-02-20drm/i915: Finish page flips and update primary planes after a GPU resetVille Syrjälä1-0/+2
2013-02-20drm/i915: Preserve the DDI link reversal configurationDamien Lespiau1-0/+1
2013-02-20drm/i915: Don't wait for page flips if there was GPU resetVille Syrjälä1-0/+3
2013-02-14drm/i915: rip out helper->disable noop functionsDaniel Vetter1-1/+0
2013-01-31drm/i915: Only run idle processing from i915_gem_retire_requests_workerChris Wilson1-2/+1
2013-01-28drm/i915: turn on the power well before suspendingPaulo Zanoni1-0/+1
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni1-1/+1
2013-01-22drm/i915: HDMI/DP - ELD info refresh support for HaswellWang Xingchao1-0/+1
2013-01-20drm/i915: Provide the quantization range in the AVI infoframeVille Syrjälä1-0/+4
2013-01-20drm/i915: Add "Automatic" mode for the "Broadcast RGB" propertyVille Syrjälä1-0/+2
2013-01-20drm/i915: Fix RGB color range property for PCH platformsVille Syrjälä1-0/+5
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