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path: root/drivers/gpu/drm/i915/intel_display.c
AgeCommit message (Expand)AuthorFilesLines
2019-03-26drm/i915: add uncore flags for unclaimed mmioDaniele Ceraolo Spurio1-1/+1
2019-03-22drm/i915/ehl: EHL outputs are different from ICLBob Paauwe1-1/+6
2019-03-21drm/i915: use intel_uncore for all forcewake get/putDaniele Ceraolo Spurio1-2/+2
2019-03-20drm/i915: Introduce i9xx_has_pps()Ville Syrjälä1-1/+9
2019-03-20drm/i915: Introduce i9xx_has_pfit()Ville Syrjälä1-2/+10
2019-03-19drm/i915: Pass dev_priv to intel_is_dual_link_lvds()Ville Syrjälä1-16/+12
2019-03-19drm/i915: Add some missing curly bracesVille Syrjälä1-4/+7
2019-03-19drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä1-2/+3
2019-03-19drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä1-2/+2
2019-03-18Merge tag 'topic/hdr-formats-2019-03-13' of git://anongit.freedesktop.org/drm...Joonas Lahtinen1-2/+27
2019-03-15drm/i915: Precompute/readout/check CHV CGM modeVille Syrjälä1-1/+7
2019-03-15drm/i915: Readout and check csc_modeVille Syrjälä1-0/+5
2019-03-15drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi1-3/+0
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi1-9/+9
2019-03-13drm/i915/icl: Implement half float formatsKevin Strasser1-0/+22
2019-03-13drm/i915: Refactor icl_is_hdr_planeKevin Strasser1-2/+5
2019-03-11Merge tag 'topic/hdr-formats-2019-03-07' of git://anongit.freedesktop.org/drm...Joonas Lahtinen1-6/+51
2019-03-11drm/i915/icl: Fix CRC mismatch error for DP link layer complianceAditya Swarup1-1/+7
2019-03-08drm/i915/crc: Make IPS workaround genericJosé Roberto de Souza1-2/+8
2019-03-08drm/i915: Compute and commit color features in fastsetsJosé Roberto de Souza1-1/+2
2019-03-06drm/i915: Simplify i830 DVO 2x clock handlingVille Syrjälä1-46/+14
2019-03-06drm/i915: Do not temporarily disable the DPLL on i830Ville Syrjälä1-2/+1
2019-03-05drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planesSwati Sharma1-0/+30
2019-03-05drm/i915: Preparations for enabling P010, P012, P016 formatsJuha-Pekka Heikkila1-6/+21
2019-03-05drm/i915: allow platforms without eDP transcoderLucas De Marchi1-1/+4
2019-03-05drm/i915: refactor transcoders reporting on error stateLucas De Marchi1-9/+12
2019-03-04drm/i915: Fix the state checker for ICL Y planesVille Syrjälä1-1/+2
2019-02-26drm/i915: Include infoframes in the crtc state dumpVille Syrjälä1-0/+26
2019-02-26drm/i915: Check infoframe state in intel_pipe_config_compare()Ville Syrjälä1-1/+48
2019-02-21drm/i915/icl: Drop redundant gamma mode maskUma Shankar1-2/+1
2019-02-20drm/i915: MEI interface implementationRamalingam C1-0/+4
2019-02-20Merge drm/drm-next into drm-intel-next-queuedJoonas Lahtinen1-8/+17
2019-02-19drm/i915: Move verify_wm_state() to heapChris Wilson1-17/+31
2019-02-18drm/i915: Restore interrupt enabling after a resetChris Wilson1-3/+0
2019-02-15drm/i915: Wrap plane update/disable hook callsVille Syrjälä1-12/+7
2019-02-15drm/i915: Add overlooked plane disable tracepoint into intel_crtc_disable_pla...Ville Syrjälä1-0/+1
2019-02-15drm/i915: Add pipe enable/disable tracepointsVille Syrjälä1-0/+4
2019-02-14Revert "drm/i915: W/A for underruns with WM1+ disabled on icl"Ville Syrjälä1-6/+0
2019-02-13drm/i915: Apply rps waitboosting for dma_fence_wait_timeout()Chris Wilson1-1/+1
2019-02-11Merge drm/drm-next into drm-misc-nextMaxime Ripard1-225/+502
2019-02-11Merge tag 'drm-intel-next-2019-02-07' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-94/+206
2019-02-08drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()Ville Syrjälä1-0/+17
2019-02-08drm/i915: Track pipe csc enable in crtc stateVille Syrjälä1-4/+14
2019-02-08drm/i915: Track pipe gamma enable/disable in crtc stateVille Syrjälä1-21/+44
2019-02-08drm/i915: Populate gamma_mode for all platformsVille Syrjälä1-1/+13
2019-02-07drm/i915: prepare for drmP.h removal from drm_modeset_helper.hSam Ravnborg1-13/+16
2019-02-07drm/i915: Move LUT programming to happen after vblank waitsVille Syrjälä1-6/+41
2019-02-07drm/i915: Split color mgmt based on single vs. double buffered registersVille Syrjälä1-7/+9
2019-02-07drm/i915: Split the gamma/csc enable bits from the plane_ctl() functionVille Syrjälä1-34/+94
2019-02-07drm/i915: Don't set update_wm_post on g4x+Ville Syrjälä1-1/+2
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