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path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2017-10-21drm/i915: Let's use more enum intel_dpll_id pll_id.Rodrigo Vivi1-16/+18
2017-10-19drm/i915: Drop the redundant hdmi prefix/suffix from a lot of variablesVille Syrjälä1-33/+30
2017-10-19drm/i915: Unify error handling for missing DDI buf trans tablesVille Syrjälä1-5/+22
2017-10-19drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handlingVille Syrjälä1-26/+34
2017-10-19drm/i915: Kill off the BXT buf_trans default_indexVille Syrjälä1-46/+34
2017-10-19drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitlyVille Syrjälä1-28/+25
2017-10-19drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()Ville Syrjälä1-24/+45
2017-10-19drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()Ville Syrjälä1-5/+4
2017-10-19drm/i915: Pass the encoder type explicitly to skl_set_iboost()Ville Syrjälä1-35/+22
2017-10-19drm/i915: Extract intel_ddi_get_buf_trans_hdmi()Ville Syrjälä1-22/+28
2017-10-19drm/i915: Relocate intel_ddi_get_buf_trans_*() functionsVille Syrjälä1-60/+55
2017-10-17drm/i915/cnl: Fix PLL mapping.Rodrigo Vivi1-2/+1
2017-10-13drm/i915: Use bdw_ddi_translations_fdi for BroadwellChris Wilson1-2/+2
2017-10-13drm/i915: Split intel_enable_ddi() into DP and HDMI variantsVille Syrjälä1-34/+46
2017-10-13drm/i915: Plumb crtc_state etc. directly to intel_ddi_pre_enable_{dp,hdmi}()Ville Syrjälä1-34/+20
2017-10-13drm/i915: Split intel_disable_ddi() into DP vs. HDMI variantsVille Syrjälä1-17/+28
2017-10-13drm/i915: Remove useless eDP check from intel_ddi_pre_enable_dp()Ville Syrjälä1-2/+2
2017-10-13drm/i915: Split intel_ddi_post_disable() into DP vs. HDMI variantsVille Syrjälä1-39/+56
2017-10-13drm/i915: Inline the required bits of intel_ddi_post_disable() into intel_ddi...Ville Syrjälä1-1/+2
2017-10-13drm/i915: Extract intel_disable_ddi_buf()Ville Syrjälä1-17/+24
2017-10-13drm/i915: Extract intel_ddi_clk_disable()Ville Syrjälä1-8/+16
2017-10-09drm/i915: avoid division by zero on cnl_calc_wrpll_linkPaulo Zanoni1-0/+3
2017-10-06drm/i915: push DDI and DSI underrun reporting on enable to encoderJani Nikula1-0/+8
2017-10-05drm/i915: avoid potential uninitialized variable useArnd Bergmann1-3/+9
2017-10-05drm/i915/mst: Use MST sideband message transactions for dpms controlDhinakaran Pandiyan1-4/+14
2017-10-03drm/i915: Fix DDI PHY init if it was already onImre Deak1-1/+2
2017-09-19drm/i915: Shrink cnl_ddi_buf_transVille Syrjälä1-5/+5
2017-09-19drm/i915: Shrink bxt_ddi_buf_transVille Syrjälä1-4/+4
2017-09-19drm/i915: Replace some spaces with tabsVille Syrjälä1-3/+3
2017-09-14drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFTManasi Navare1-1/+1
2017-08-31drm/i915/cnl: Fix DP max voltageRodrigo Vivi1-4/+11
2017-08-31drm/i915/cnl: Fix DDI hdmi level selection.Rodrigo Vivi1-1/+4
2017-08-31drm/i915/cnl: Move ddi buf trans related functions up.Rodrigo Vivi1-61/+61
2017-08-31drm/i915/cnl: Move voltage check into ddi buf trans functions.Rodrigo Vivi1-27/+21
2017-08-31drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.Rodrigo Vivi1-1/+6
2017-08-31drm/i915: Align vswing sequences with old ddi buffer registers.Rodrigo Vivi1-12/+10
2017-08-31drm/i915: decouple gen9 and gen10 dp signal levels.Rodrigo Vivi1-9/+18
2017-08-31drm/i915: Introduce intel_ddi_dp_level.Rodrigo Vivi1-6/+10
2017-08-22drm/i915: Constify states passed to enable/disable/etc. encoder hooksVille Syrjälä1-15/+15
2017-08-22drm/i915: Plumb crtc_state to PSR enable/disableVille Syrjälä1-2/+2
2017-08-22drm/i915: Init infoframe vfuncs for DP encoders as wellVille Syrjälä1-0/+2
2017-08-22drm/i915: Move infoframe vfuncs into intel_digital_portVille Syrjälä1-12/+10
2017-08-22drm/i915: Disable infoframes when shutting down DDI HDMIVille Syrjälä1-3/+12
2017-08-22drm/i915: Check has_infoframes when enabling infoframesVille Syrjälä1-3/+3
2017-08-11drm/i915: Return correct EDP voltage swing table for 0.85VMatthias Kaehlcke1-1/+1
2017-07-27drm/i915/cnl: Fix loadgen select programming on ddi vswing sequenceNavare, Manasi D1-2/+2
2017-07-27drm/i915: prepare pipe for YCBCR420 outputShashank Sharma1-0/+3
2017-07-11drm/i915/cnl: Add missing type case.Rodrigo Vivi1-1/+4
2017-07-07drm/i915/cnl: Get DDI clock based on PLLs.Rodrigo Vivi1-0/+111
2017-06-20drm/i915/cnl: Fix RMW on ddi vswing sequence.Rodrigo Vivi1-0/+7
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