summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2015-09-01drm/i915: Don't use link_bw for PLL setupVille Syrjälä1-7/+4
2015-08-26drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi1-50/+25
2015-08-14drm/i915: Per-DDI I_boost overrideAntti Koskipaa1-8/+30
2015-08-14drm/i915: Set alternate aux for DDI-ERodrigo Vivi1-3/+2
2015-07-06drm/i915: set FDI translations to NULL on SKLPaulo Zanoni1-0/+1
2015-07-06drm/i915/bxt: BUNs related to port PLLVandana Kannan1-10/+5
2015-07-06drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä1-25/+24
2015-07-03drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak1-0/+20
2015-06-30drm/i915/bxt: add DDI port HW readout supportImre Deak1-2/+20
2015-06-30drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak1-3/+13
2015-06-30drm/i915/skl: Buffer translation improvementsDavid Weinehall1-115/+394
2015-06-26drm/i915/skl: Skip remaining dividers when deviation is 0Damien Lespiau1-1/+8
2015-06-26drm/i915/skl: Prefer even dividers for SKL DPLLsDamien Lespiau1-0/+7
2015-06-26drm/i915/skl: Replace the HDMI DPLL divider computation algorithmDamien Lespiau1-74/+137
2015-06-12drm/i915/bxt: fix DDI PHY vswing scale value settingImre Deak1-18/+18
2015-06-12drm/i915: Don't display the boot CDCLK twiceDamien Lespiau1-4/+3
2015-06-03drm/i915/bxt: edp1.4 Intermediate Freq supportSonika Jindal1-23/+16
2015-05-29drm/i915/skl: Don't try to store the wrong central frequencyDamien Lespiau1-2/+0
2015-05-29drm/i915: Correctly prefix HSW/BDW HDMI clock functionsDamien Lespiau1-13/+12
2015-05-29drm/i915/skl: Remove unnecessary () used with abs_diff()Damien Lespiau1-1/+1
2015-05-29drm/i915/skl: Remove unnecessary () used with div_u64()Damien Lespiau1-3/+3
2015-05-29drm/i915/skl: Factor out computing the DPLL paramaters from the dividersDamien Lespiau1-64/+75
2015-05-29drm/i915/skl: Use a more idomatic early returnDamien Lespiau1-62/+59
2015-05-29drm/i915/skl: Propagate the error if we fail to find a suitable DPLL dividerDamien Lespiau1-2/+6
2015-05-29drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failingDamien Lespiau1-1/+2
2015-05-29drm/i915/skl: Make sure to break when not finding suitable PLL dividersDamien Lespiau1-0/+4
2015-05-29drm/i915: remove useless DP and DDI encoder ->hot_plug hooksJani Nikula1-15/+0
2015-05-29drm/i915: group all hotplug related fields into a new struct in dev_privJani Nikula1-1/+1
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau1-2/+6
2015-05-20drm/i915/bxt: Move around lane stagger calculationVandana Kannan1-20/+20
2015-05-20drm/i915/bxt: Port PLL programming BUNVandana Kannan1-23/+56
2015-05-20drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira1-0/+9
2015-05-08drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau1-32/+32
2015-05-08drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira1-4/+5
2015-05-08drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal1-1/+1
2015-05-08drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau1-13/+13
2015-04-30drm/i915: fix intel_prepare_ddiImre Deak1-10/+18
2015-04-30drm/i915: factor out ddi_get_encoder_portImre Deak1-9/+19
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan1-1/+119
2015-04-16drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau1-0/+9
2015-04-16drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau1-4/+12
2015-04-16drm/i915/bxt: Determine programmed frequencySatheeshakrishna M1-1/+29
2015-04-16drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M1-1/+1
2015-04-16drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M1-0/+129
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M1-0/+165
2015-04-16drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M1-2/+2
2015-04-16drm/i915/skl: Add back HDMI translation tableSonika Jindal1-10/+12
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan1-0/+125
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan1-0/+2
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter1-1/+1
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-30 19:11:50 +0300