summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau1-2/+6
2015-05-20drm/i915/bxt: Move around lane stagger calculationVandana Kannan1-20/+20
2015-05-20drm/i915/bxt: Port PLL programming BUNVandana Kannan1-23/+56
2015-05-20drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira1-0/+9
2015-05-08drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau1-32/+32
2015-05-08drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira1-4/+5
2015-05-08drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal1-1/+1
2015-05-08drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau1-13/+13
2015-04-30drm/i915: fix intel_prepare_ddiImre Deak1-10/+18
2015-04-30drm/i915: factor out ddi_get_encoder_portImre Deak1-9/+19
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan1-1/+119
2015-04-16drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau1-0/+9
2015-04-16drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau1-4/+12
2015-04-16drm/i915/bxt: Determine programmed frequencySatheeshakrishna M1-1/+29
2015-04-16drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M1-1/+1
2015-04-16drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M1-0/+129
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M1-0/+165
2015-04-16drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M1-2/+2
2015-04-16drm/i915/skl: Add back HDMI translation tableSonika Jindal1-10/+12
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan1-0/+125
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan1-0/+2
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter1-1/+1
2015-04-13drm/i915: Allocate connector state together with the connectorsAnder Conselvan de Oliveira1-2/+2
2015-04-09drm/i915/bxt: Increase DDI buf idle timeoutVandana Kannan1-1/+1
2015-03-31drm/i915: Convert the ddi cdclk code to get_display_clock_speedVille Syrjälä1-100/+1
2015-03-26drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder()Ander Conselvan de Oliveira1-9/+15
2015-03-18drm/i915/skl: Add support for edp 1.4 intermediate frequenciesSonika Jindal1-0/+9
2015-03-18drm/i915/skl: Only use the 800mV+2bB HDMI translation entryDamien Lespiau1-16/+14
2015-02-25drm/i915/skl: Add support for edp1.4 low vswingSonika Jindal1-6/+40
2015-01-30drm/i915: Use pipe_config's cpu_transcoder for reading encoder hw stateAnder Conselvan de Oliveira1-1/+1
2015-01-27drm/i915: Enable/disable DRRSVandana Kannan1-0/+2
2015-01-27drm/i915: Make intel_crtc->config a pointerAnder Conselvan de Oliveira1-26/+26
2015-01-27drm/i915: Pass new_config down do crtc_compute_clockAnder Conselvan de Oliveira1-12/+17
2015-01-27drm/i915: Embedded struct drm_crtc_state in intel_crtc_stateAnder Conselvan de Oliveira1-9/+9
2015-01-27drm/i915: Rename struct intel_crtc_config to intel_crtc_stateAnder Conselvan de Oliveira1-5/+5
2014-12-15drm/i915: Consolidate DDI clock reading out in a single functionDamien Lespiau1-6/+7
2014-12-03drm/i915/skl: Update the DDI translation values for DP/eDP 1.3Damien Lespiau1-6/+6
2014-11-21drm/i915: Don't rely upon encoder->type for infoframe hw state readoutDaniel Vetter1-8/+5
2014-11-19drm/i915/ddi: set has_infoframe flag on DDI too v2Jesse Barnes1-0/+8
2014-11-18drm/i915/ddi: add break in DDI mode select switchJesse Barnes1-0/+1
2014-11-17drm/i915/skl: Use the pipe config DPLL tracking to query the link clockDamien Lespiau1-5/+1
2014-11-17drm/i915/skl: Set the eDP link rate on DPLL0Damien Lespiau1-0/+20
2014-11-17drm/i915: Introduce intel_psr.cRodrigo Vivi1-2/+2
2014-11-14drm/i915/skl: Fix big integer constant sparse warningDamien Lespiau1-4/+6
2014-11-14drm/i915/skl: Apply eDP WA only for gen < 9Vandana Kannan1-2/+2
2014-11-14drm/i915/skl: Implementation of SKL DPLL programmingSatheeshakrishna M1-1/+225
2014-11-14drm/i915/skl: Adjust the port PLL selection codeSatheeshakrishna M1-5/+25
2014-11-14drm/i915/skl: Define shared DPLLs for SkylakeSatheeshakrishna M1-1/+125
2014-11-14drm/i915/skl: Determine enabled PLL and its linkrate/pixel clockSatheeshakrishna M1-1/+114
2014-11-14drm/i915/skl: CD clock back calculation for SKLSatheeshakrishna M1-9/+66
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-04 02:49:52 +0300