summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_cdclk.c
AgeCommit message (Expand)AuthorFilesLines
2018-02-14drm/i915/vlv: Add cdclk workaround for DSIHans de Goede1-0/+8
2018-02-06drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak1-5/+17
2018-01-18BackMerge tag 'v4.15-rc8' into drm-nextDave Airlie1-9/+26
2018-01-04drm/i915: Apply Display WA #1183 on skl, kbl, and cflLucas De Marchi1-9/+26
2017-11-30drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.Maarten Lankhorst1-1/+1
2017-10-25drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.Rodrigo Vivi1-12/+2
2017-10-25drm/i915: Perform a central cdclk state sanity checkVille Syrjälä1-11/+19
2017-10-25drm/i915: Sanity check cdclk in vlv_set_cdclk()Ville Syrjälä1-0/+12
2017-10-25drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä1-1/+45
2017-10-25drm/i915: Use cdclk_state->voltage on CNLVille Syrjälä1-16/+31
2017-10-25drm/i915: Use cdclk_state->voltage on BXT/GLKVille Syrjälä1-2/+21
2017-10-25drm/i915: Use cdclk_state->voltage on SKL/KBL/CFLVille Syrjälä1-7/+36
2017-10-25drm/i915: Use cdclk_state->voltage on BDWVille Syrjälä1-6/+29
2017-10-25drm/i915: Use cdclk_state->voltage on VLV/CHVVille Syrjälä1-16/+38
2017-10-25drm/i915: Start tracking voltage level in the cdclk stateVille Syrjälä1-7/+24
2017-10-25drm/i915: Clean up some cdclk switch statementsVille Syrjälä1-34/+34
2017-10-11drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lockSagar Arun Kamble1-20/+20
2017-09-12drm/i915: Increase poll time for BDW FCLK_DONEMarta Lofstedt1-1/+5
2017-08-31drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()Ville Syrjälä1-52/+44
2017-08-31drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"Ville Syrjälä1-98/+104
2017-06-29drm/i915: reintroduce VLV/CHV PFI programming power domain workaroundGabriel Krisman Bertazi1-0/+20
2017-06-12drm/i915/cnl: Allow dynamic cdclk changes on CNLRodrigo Vivi1-4/+56
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä1-1/+107
2017-06-12drm/i915/cnl: Implement .set_cdclk() for CNLVille Syrjälä1-0/+106
2017-06-12drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä1-1/+55
2017-06-02drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi1-1/+28
2017-05-05drm/i915: Fix rawclk readout for g4xVille Syrjälä1-4/+2
2017-04-06drm/i915/glk: limit pixel clock to 99% of cdclk workaroundMadhav Chauhan1-3/+13
2017-03-22drm/i915: Implement cdclk restrictions based on Azalia BCLKPandiyan, Dhinakaran1-0/+12
2017-03-22drm/i915/glk: Apply cdclk workaround for DP audioPandiyan, Dhinakaran1-6/+11
2017-03-13drm/i915: Use new atomic iterator macros in cdclkMaarten Lankhorst1-1/+1
2017-03-07drm/i915: remove potentially confusing IS_G4X checksPaulo Zanoni1-2/+2
2017-02-08drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cd...Ville Syrjälä1-46/+33
2017-02-08drm/i915: Nuke the VLV/CHV PFI programming power domain workaroundVille Syrjälä1-14/+0
2017-02-08drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()Ville Syrjälä1-1/+4
2017-02-08drm/i915: Pass the cdclk state to the set_cdclk() functionsVille Syrjälä1-30/+48
2017-02-08drm/i915: Pass dev_priv to remainder of the cdclk functionsVille Syrjälä1-15/+10
2017-02-08drm/i915: Track full cdclk state for the logical and actual cdclk frequenciesVille Syrjälä1-45/+78
2017-02-08drm/i915: Start moving the cdclk stuff into a distinct state structureVille Syrjälä1-156/+226
2017-02-08drm/i915: Pass computed vco to bxt_set_cdclk()Ville Syrjälä1-14/+19
2017-02-08drm/i915: Move most cdclk/rawclk related code to intel_cdclk.cVille Syrjälä1-0/+1794
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 07:43:49 +0300