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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2018-10-22drm/i915/icl: Define DSI panel programming registersMadhav Chauhan1-0/+38
2018-10-22drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan1-0/+8
2018-10-22drm/i915/icl: Define DSI transcoder timing registersMadhav Chauhan1-0/+14
2018-10-22drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan1-0/+17
2018-10-22drm/i915/icl: Define TRANS_DSI_FUNC_CONF registerMadhav Chauhan1-0/+45
2018-10-22drm/i915/icl: Add macros for MMIO of DSI transcoder registersMadhav Chauhan1-0/+4
2018-10-16drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar1-0/+3
2018-10-16drm/i915/icl: Introduce new macros to get combophy registersLucas De Marchi1-104/+59
2018-10-16drm/i915/icl: Combine all port/combophy macros at one placeMahesh Kumar1-65/+72
2018-10-16drm/i915/icl: apply Display WA #1178 to fix type C donglesLucas De Marchi1-0/+9
2018-10-15drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCONShashank Sharma1-0/+2
2018-10-09drm/i915/icl:Add Wa_1606682166Anuj Phogat1-0/+1
2018-10-09drm/i915/icl: Add Wa_1406609255Radhakrishna Sripada1-0/+3
2018-10-06drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICLJosé Roberto de Souza1-2/+2
2018-10-02drm/i915: Add plane alpha blending support, v2.Maarten Lankhorst1-0/+2
2018-09-26drm/i915/icl: Define TA_TIMING_PARAM registersMadhav Chauhan1-0/+23
2018-09-26drm/i915/icl: Define data/clock lanes dphy timing registersMadhav Chauhan1-0/+58
2018-09-21drm/i915: Clean up scaler setup, v2.Maarten Lankhorst1-3/+4
2018-09-14drm/i915/skl+: Decode memory bandwidth and parametersMahesh Kumar1-0/+18
2018-09-14drm/i915/bxt: Decode memory bandwidth and parametersMahesh Kumar1-0/+30
2018-09-11drm/i915/icl: Define T_INIT_MASTER registersMadhav Chauhan1-0/+6
2018-09-04drm/i915/icl: Fix context RPCS programmingTvrtko Ursulin1-0/+2
2018-08-29drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engineManasi Navare1-2/+2
2018-08-24drm/i915/icl: implement the tc/legacy HPD {dis,}connect flowsPaulo Zanoni1-0/+6
2018-08-23drm/i915: Rename PLANE_CTL_DECOMPRESSION_ENABLEDhinakaran Pandiyan1-1/+1
2018-08-21drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare1-0/+5
2018-08-21drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare1-1/+4
2018-08-16drm/i915: remove confusing GPIO vs PCH_GPIOLucas De Marchi1-19/+5
2018-08-16drm/i915: make PCH_GMBUS* definitions private to gvtLucas De Marchi1-7/+0
2018-08-14drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula1-0/+1
2018-08-08drm/i915/icl: Add missing power gate enumsImre Deak1-0/+2
2018-08-08drm/i915: Use existing power well IDs where possibleImre Deak1-3/+0
2018-08-08drm/i915: Make power well ID names more uniformImre Deak1-5/+5
2018-08-08drm/i915: Remove redundant power well IDsImre Deak1-105/+13
2018-08-08drm/i915/ddi: Use power well CTL IDX instead of IDImre Deak1-44/+84
2018-08-08drm/i915/vlv: Use power well CTL IDX instead of IDImre Deak1-5/+17
2018-08-03drm/i915: Clear all residual RPS events on disabling interruptsChris Wilson1-2/+4
2018-08-01Revert "drm/i915/icl: WaEnableFloatBlendOptimization"Mika Kuoppala1-3/+0
2018-07-28drm/i915/icl: Set TBT IO in Aux transactionAnusha Srivatsa1-0/+1
2018-07-25drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni1-0/+20
2018-07-25drm/i915/icl: program MG_DP_MODEPaulo Zanoni1-0/+15
2018-07-25drm/i915/icl: Update FIA supported lane count for hpd.Animesh Manna1-0/+3
2018-07-25drm/i915/icl: implement icl_digital_port_connected()Paulo Zanoni1-0/+8
2018-07-25drm/i915/icl: Add remaining registers and bitfields for MG PHY DDIManasi Navare1-113/+157
2018-07-21drm/i915/dsc: Add missing _MMIO() from PPS registersAnusha Srivatsa1-38/+38
2018-07-19i915/dp/dsc: Add Rate Control Range Parameter RegistersAnusha Srivatsa1-0/+104
2018-07-19i915/dp/dsc: Add Rate Control Buffer Threshold RegistersAnusha Srivatsa1-0/+51
2018-07-19i915/dp/dsc: Add DSC PPS register definitionsAnusha Srivatsa1-0/+255
2018-07-19drm/i915/icl: Add VIDEO_DIP registersAnusha Srivatsa1-0/+23
2018-07-12drm/i915/gmbus: Enable burst readRamalingam C1-0/+1
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