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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2013-10-03drm/i915: Tweak RPS thresholds to more aggressively downclockChris Wilson1-1/+1
2013-10-03drm/i915/hsw: Disable L3 caching of atomic memory operations.Francisco Jerez1-0/+6
2013-10-01drm/i915/vlv: use correct units for rc6 residency v2Jesse Barnes1-0/+3
2013-10-01drm/i915/vlv: use lower precision RC6 counterJesse Barnes1-0/+4
2013-10-01drm/i915: Program GMBUS Frequency based on the CDCLK for VLV.Chon Ming Lee1-0/+8
2013-10-01drm/i915: precendence bug in GT_PARITY_ERROR()Dan Carpenter1-1/+1
2013-10-01drm/i915: Calculate PSR register offsets from base + genBen Widawsky1-10/+11
2013-09-19drm/i915: Add second slice l3 remappingBen Widawsky1-0/+7
2013-09-19drm/i915: write D_COMP using the mailboxPaulo Zanoni1-0/+4
2013-09-17drm/i915: Fix port_clock and adjusted_mode.clock readout all overVille Syrjälä1-0/+1
2013-09-06drm/i915: clean up power sequencing register port select definitionsJani Nikula1-6/+2
2013-09-04drm/i915: Report enabled slices on Haswell GT3Rodrigo Vivi1-0/+5
2013-09-04drm/i915: add VLV DSI PLL Calculationsymohanma1-0/+32
2013-09-04drm/i915: add MIPI DSI register definitionsJani Nikula1-0/+410
2013-09-04drm/i915: add VLV pipeconf bit definition for DSI PLL lockJani Nikula1-0/+1
2013-09-04drm/i915: add more VLV IOSF sideband ports accessorsJani Nikula1-0/+4
2013-09-03drm/i915: enable trickle feed on HaswellPaulo Zanoni1-0/+1
2013-09-03x86: add early quirk for reserving Intel graphics stolen memory v5Jesse Barnes1-15/+0
2013-09-03drm/i915: Use RCS flips on Ivybridge+Chris Wilson1-0/+18
2013-09-02Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux int...Dave Airlie1-4/+12
2013-08-30Merge tag 'drm-intel-next-2013-08-23' of git://people.freedesktop.org/~danvet...Dave Airlie1-10/+19
2013-08-30drm/i915/hdmi: Write HDMI vendor specific infoframesLespiau, Damien1-0/+2
2013-08-30drm/i915: ivb: fix edp voltage swing reg valImre Deak1-1/+1
2013-08-23drm/i915: Fix context size calculation on SNB/IVB/VLVVille Syrjälä1-8/+15
2013-08-23drm/i915: Expose energy counter on SNB+ through debugfsJesse Barnes1-0/+2
2013-08-22drm/i915: clarify Haswell power well bit namesPaulo Zanoni1-2/+2
2013-08-18drm/i915: Invalidate TLBs for the rings after a resetChris Wilson1-0/+2
2013-08-07drm/i915: fix gen4 digital port hotplug definitionsDaniel Vetter1-3/+9
2013-08-05drm/i915: Use the watermark latency values from dev_priv for ILK/SNB/IVB tooVille Syrjälä1-9/+0
2013-07-26drm/i915: fix pnv display core clock readout outDaniel Vetter1-0/+6
2013-07-24drm/i915: add functions to disable and restore LCPLLPaulo Zanoni1-0/+15
2013-07-24drm/i915: extend lpt_enable_clkout_dpPaulo Zanoni1-1/+2
2013-07-19drm/i915: kill Ivybridge vblank irq vfuncsPaulo Zanoni1-0/+3
2013-07-18drm/i915: Match all PSR mode entry conditions before enabling it.Rodrigo Vivi1-0/+7
2013-07-18drm/i915: Added debugfs support for PSR StatusRodrigo Vivi1-0/+24
2013-07-18drm/i915: Enable/Disable PSRRodrigo Vivi1-0/+42
2013-07-16drm/i915: Define some of the eLLC magicBen Widawsky1-0/+4
2013-07-11drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reportingDaniel Vetter1-0/+1
2013-07-11drm/i915: improve SERR_INT clearing for fifo underrun reportingDaniel Vetter1-0/+1
2013-07-09drm/i915: fix dvo DPLL regressionDaniel Vetter1-1/+2
2013-07-02drm/i915: Use wait_for() to wait for Punit to change GPU freq on VLVVille Syrjälä1-0/+1
2013-07-01drm/i915: Fix context sizes on HSWBen Widawsky1-8/+7
2013-07-01drm/i915: Fix VLV sprite register offsetsVille Syrjälä1-25/+25
2013-07-01drm/i915: s/LFP/LPF in DPIO PLL register namesVille Syrjälä1-3/+3
2013-07-01drm/i915: Fix up sdvo hpd pins for i965g/gmDaniel Vetter1-7/+6
2013-06-18drm/i915: explicitly set up PIPECONF (and gamma table) on haswellDaniel Vetter1-3/+3
2013-06-13drm/i915: Try harder to disable trickle feed on VLVVille Syrjälä1-0/+2
2013-06-10drm/i915: scrap register address storageDaniel Vetter1-3/+3
2013-06-10drm/i915: refactor PCH_DPLL_SEL #definesDaniel Vetter1-9/+3
2013-06-07drm/i915: WA: FBC Render Nuke.Rodrigo Vivi1-0/+4
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