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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2014-08-07drm/i915: Fix drain latency precision multipler for VLVZhenyu Wang1-25/+25
2014-08-05Merge tag 'v3.16' into drm-nextDave Airlie1-0/+3
2014-07-29Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter1-2/+9
2014-07-21drm/i915: add some registers need for displayport MST support.Dave Airlie1-2/+9
2014-07-12drm/i915/chv: calculate rc6 residency correctlyMika Kuoppala1-1/+1
2014-07-11drm/i915: populate mem_freq/cz_clock for chvDeepak S1-0/+6
2014-07-11drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout support for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout and cross-checking for ddi_pll_selDaniel Vetter1-0/+1
2014-07-11drm/i915: Clean up WRPLL/SPLL #definesDaniel Vetter1-3/+4
2014-07-10drm/i915: fix D_COMP usage on BDWPaulo Zanoni1-1/+4
2014-07-09drm/i915: Don't clobber the GTT when it's within stolen memoryVille Syrjälä1-0/+3
2014-07-08drm/i915/vlv: WA for Turbo and RC6 to work together.Deepak S1-0/+11
2014-07-08drm/i915/bdw: implement semaphore waitBen Widawsky1-0/+3
2014-07-08drm/i915/bdw: implement semaphore signalBen Widawsky1-1/+4
2014-07-07drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bitsVille Syrjälä1-0/+5
2014-06-18drm/i915: Add some L3 registers to the parser whitelistBrad Volkin1-0/+2
2014-06-16drm/i915: update BDW DDI buffer translationsPaulo Zanoni1-11/+0
2014-06-13drm/i915: BDW PSR: Add single frame update support.Rodrigo Vivi1-0/+1
2014-06-13drm/i915: Fix VLV CRC reading.Rodrigo Vivi1-1/+1
2014-06-11drm/i915: Add #defines for short/long pulse on gmch platformsDaniel Vetter1-0/+6
2014-06-11drm/i915: Use transcoder as index to MIPI regsShashank Sharma1-47/+93
2014-06-11drm/i915: Change Mipi register definitionsShashank Sharma1-90/+93
2014-06-11drm/i915/chv: Handle video DIP registers on CHVVille Syrjälä1-5/+12
2014-06-11drm/i915: Don't use pipe_offset stuff for DPLL registersVille Syrjälä1-16/+10
2014-06-11drm/i915/chv: Force clock buffer enablesVille Syrjälä1-0/+18
2014-06-11drm/i915/chv: Try to program the PHY used clock channel overridesVille Syrjälä1-0/+7
2014-06-11drm/i915/chv: Enable RPS (Turbo) for CherryviewDeepak S1-0/+11
2014-06-11drm/i915/chv: Enable Render Standby (RC6) for CherryviewDeepak S1-0/+2
2014-06-05drm/i915: Enable interrupt-based AGPBUSY# enable on 85xVille Syrjälä1-0/+4
2014-06-05drm/i915: Flip the sense of AGPBUSY_DIS bitVille Syrjälä1-1/+1
2014-05-22drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä1-0/+4
2014-05-22drm/i915: Add a brief description of the VLV display PHY internalsVille Syrjälä1-4/+81
2014-05-21drm/i915: Fix mmio vs. CS flip race on ILK+Ville Syrjälä1-0/+1
2014-05-20drm/i915: Drop /** */ comments from i915_reg.hVille Syrjälä1-123/+123
2014-05-20drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä1-0/+3
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä1-0/+7
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä1-0/+11
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä1-0/+14
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Register port D encoders and connectorsVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä1-0/+2
2014-05-20drm/i915/chv: Add cursor pipe offsetsVille Syrjälä1-12/+18
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Add CHV display supportRafael Barbalho1-3/+8
2014-05-20drm/i915: Fix ILK GPU reset domain bitsVille Syrjälä1-1/+7
2014-05-19drm/i915: Add MIPI mmio reg baseShashank Sharma1-0/+1
2014-05-19drm/i915: rename IOSF sideband opcodes according to the specImre Deak1-5/+0
2014-05-16drm/i915: Enable PM Interrupts target via Display Interface.Deepak S1-0/+1
2014-05-16drm/i915/bdw: Implement a basic PM interrupt handlerBen Widawsky1-0/+1
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