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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2014-08-13drm/i915: Add support for variable cursor size on 845/865Ville Syrjälä1-1/+2
2014-08-12drm/i915/bdw: Interrupts with logical ringsOscar Mateo1-0/+2
2014-08-12drm/i915/bdw: GEN-specific logical ring emit requestOscar Mateo1-0/+1
2014-08-11drm/i915/bdw: Populate LR contexts (somewhat)Oscar Mateo1-0/+1
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat1-6/+3
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat1-0/+1
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä1-5/+2
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä1-41/+13
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä1-15/+123
2014-08-08drm/i915: Add 180 degree sprite rotation supportVille Syrjälä1-0/+3
2014-08-08drm/i915: remove duplicate register definesPaulo Zanoni1-2/+0
2014-08-08drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi1-0/+1
2014-08-08drm/i915: Clarify CHV swing margin/deemph bitsVille Syrjälä1-2/+6
2014-08-08drm/i915: Add cdclk change support for chvVille Syrjälä1-0/+4
2014-08-08drm/i915: Add DP training pattern 3 for CHVVille Syrjälä1-0/+2
2014-08-08drm/i915: Add chv port D TX wellsVille Syrjälä1-0/+4
2014-08-08drm/i915: Add per-pipe power wells for chvVille Syrjälä1-0/+12
2014-08-08drm/i915: Add chv cmnlane power wellsVille Syrjälä1-0/+1
2014-08-07drm/i915: Fix drain latency precision multipler for VLVZhenyu Wang1-25/+25
2014-08-05Merge tag 'v3.16' into drm-nextDave Airlie1-0/+3
2014-07-29Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter1-2/+9
2014-07-21drm/i915: add some registers need for displayport MST support.Dave Airlie1-2/+9
2014-07-12drm/i915/chv: calculate rc6 residency correctlyMika Kuoppala1-1/+1
2014-07-11drm/i915: populate mem_freq/cz_clock for chvDeepak S1-0/+6
2014-07-11drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout support for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout and cross-checking for ddi_pll_selDaniel Vetter1-0/+1
2014-07-11drm/i915: Clean up WRPLL/SPLL #definesDaniel Vetter1-3/+4
2014-07-10drm/i915: fix D_COMP usage on BDWPaulo Zanoni1-1/+4
2014-07-09drm/i915: Don't clobber the GTT when it's within stolen memoryVille Syrjälä1-0/+3
2014-07-08drm/i915/vlv: WA for Turbo and RC6 to work together.Deepak S1-0/+11
2014-07-08drm/i915/bdw: implement semaphore waitBen Widawsky1-0/+3
2014-07-08drm/i915/bdw: implement semaphore signalBen Widawsky1-1/+4
2014-07-07drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bitsVille Syrjälä1-0/+5
2014-06-18drm/i915: Add some L3 registers to the parser whitelistBrad Volkin1-0/+2
2014-06-16drm/i915: update BDW DDI buffer translationsPaulo Zanoni1-11/+0
2014-06-13drm/i915: BDW PSR: Add single frame update support.Rodrigo Vivi1-0/+1
2014-06-13drm/i915: Fix VLV CRC reading.Rodrigo Vivi1-1/+1
2014-06-11drm/i915: Add #defines for short/long pulse on gmch platformsDaniel Vetter1-0/+6
2014-06-11drm/i915: Use transcoder as index to MIPI regsShashank Sharma1-47/+93
2014-06-11drm/i915: Change Mipi register definitionsShashank Sharma1-90/+93
2014-06-11drm/i915/chv: Handle video DIP registers on CHVVille Syrjälä1-5/+12
2014-06-11drm/i915: Don't use pipe_offset stuff for DPLL registersVille Syrjälä1-16/+10
2014-06-11drm/i915/chv: Force clock buffer enablesVille Syrjälä1-0/+18
2014-06-11drm/i915/chv: Try to program the PHY used clock channel overridesVille Syrjälä1-0/+7
2014-06-11drm/i915/chv: Enable RPS (Turbo) for CherryviewDeepak S1-0/+11
2014-06-11drm/i915/chv: Enable Render Standby (RC6) for CherryviewDeepak S1-0/+2
2014-06-05drm/i915: Enable interrupt-based AGPBUSY# enable on 85xVille Syrjälä1-0/+4
2014-06-05drm/i915: Flip the sense of AGPBUSY_DIS bitVille Syrjälä1-1/+1
2014-05-22drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä1-0/+4
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