| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-06-05 | drm/i915: Enable interrupt-based AGPBUSY# enable on 85x | Ville Syrjälä | 1 | -0/+4 |
| 2014-06-05 | drm/i915: Flip the sense of AGPBUSY_DIS bit | Ville Syrjälä | 1 | -1/+1 |
| 2014-05-22 | drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk | Ville Syrjälä | 1 | -0/+4 |
| 2014-05-22 | drm/i915: Add a brief description of the VLV display PHY internals | Ville Syrjälä | 1 | -4/+81 |
| 2014-05-21 | drm/i915: Fix mmio vs. CS flip race on ILK+ | Ville Syrjälä | 1 | -0/+1 |
| 2014-05-20 | drm/i915: Drop /** */ comments from i915_reg.h | Ville Syrjälä | 1 | -123/+123 |
| 2014-05-20 | drm/i915/chv: Add a bunch of pre production workarounds | Ville Syrjälä | 1 | -0/+3 |
| 2014-05-20 | drm/i915/chv: Use RMW to toggle swing calc init | Ville Syrjälä | 1 | -0/+7 |
| 2014-05-20 | drm/i915/chv: Don't do group access reads from TX lanes either | Ville Syrjälä | 1 | -0/+11 |
| 2014-05-20 | drm/i915/chv: Don't use PCS group access reads | Ville Syrjälä | 1 | -0/+14 |
| 2014-05-20 | drm/i915/chv: Set soft reset override bit for data lane resets | Ville Syrjälä | 1 | -0/+1 |
| 2014-05-20 | drm/i915/chv: Register port D encoders and connectors | Ville Syrjälä | 1 | -0/+1 |
| 2014-05-20 | drm/i915/chv: Fix PORT_TO_PIPE for CHV | Ville Syrjälä | 1 | -0/+2 |
| 2014-05-20 | drm/i915/chv: Add cursor pipe offsets | Ville Syrjälä | 1 | -12/+18 |
| 2014-05-20 | drm/i915/chv: Fix gmbus for port D | Ville Syrjälä | 1 | -0/+1 |
| 2014-05-20 | drm/i915/chv: Add CHV display support | Rafael Barbalho | 1 | -3/+8 |
| 2014-05-20 | drm/i915: Fix ILK GPU reset domain bits | Ville Syrjälä | 1 | -1/+7 |
| 2014-05-19 | drm/i915: Add MIPI mmio reg base | Shashank Sharma | 1 | -0/+1 |
| 2014-05-19 | drm/i915: rename IOSF sideband opcodes according to the spec | Imre Deak | 1 | -5/+0 |
| 2014-05-16 | drm/i915: Enable PM Interrupts target via Display Interface. | Deepak S | 1 | -0/+1 |
| 2014-05-16 | drm/i915/bdw: Implement a basic PM interrupt handler | Ben Widawsky | 1 | -0/+1 |
| 2014-05-12 | drm/i915/chv: Pipe select change for DP and HDMI | Chon Ming Lee | 1 | -0/+6 |
| 2014-05-12 | drm/i915/chv: Add update and enable pll for Cherryview | Chon Ming Lee | 1 | -0/+70 |
| 2014-05-12 | drm/i915/chv: Trigger phy common lane reset | Chon Ming Lee | 1 | -0/+8 |
| 2014-05-12 | drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2 | Chon Ming Lee | 1 | -0/+6 |
| 2014-05-12 | drm/i915/chv: Add DPIO offset for Cherryview. v3 | Chon Ming Lee | 1 | -0/+1 |
| 2014-05-12 | drm/i915/chv: Add DDL register defines for Cherryview | Ville Syrjälä | 1 | -0/+29 |
| 2014-05-07 | drm/i915: add various missing GTI/Gunit register definitions | Imre Deak | 1 | -1/+40 |
| 2014-05-06 | drm/i915/chv: Add DPINVGTT registers defines for Cherryview | Ville Syrjälä | 1 | -1/+11 |
| 2014-05-06 | drm/i915/chv: Add display interrupt registers bits for Cherryview | Ville Syrjälä | 1 | -1/+20 |
| 2014-05-06 | drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview | Ville Syrjälä | 1 | -0/+7 |
| 2014-05-06 | drm/i915/chv: Add PIPESTAT register bits for Cherryview | Ville Syrjälä | 1 | -0/+8 |
| 2014-05-05 | drm/i915: vlv: add RC6 residency counters | Imre Deak | 1 | -0/+3 |
| 2014-05-05 | drm/i915: vlv: clean up GTLC wake control/status register macros | Imre Deak | 1 | -2/+8 |
| 2014-05-05 | drm/i915:Initialize the second BSD ring on BDW GT3 machine | Zhao Yakui | 1 | -0/+1 |
| 2014-04-10 | drm/i915: Add support for DRRS to switch RR | Pradeep Bhat | 1 | -0/+1 |
| 2014-04-09 | drm/i915: Add more registers to the whitelist for mesa | Brad Volkin | 1 | -0/+9 |
| 2014-04-09 | drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONE | Damien Lespiau | 1 | -1/+1 |
| 2014-04-09 | drm/i915/bdw: Provide a gen8 version of SRM | Damien Lespiau | 1 | -0/+1 |
| 2014-04-09 | drm/i915: Protect the argument expansion in LRI and SRM macros | Damien Lespiau | 1 | -2/+2 |
| 2014-04-09 | drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' | Akash Goel | 1 | -0/+1 |
| 2014-04-03 | drm/i915: Move all ring resets before setting the HWS page | Chris Wilson | 1 | -0/+1 |
| 2014-04-03 | drm/i915: Fix framecount offset | Rafael Barbalho | 1 | -3/+3 |
| 2014-04-02 | drm/i915/bdw: Expand FADD to 64bit | Ben Widawsky | 1 | -0/+1 |
| 2014-04-02 | drm/i915: Add OACONTROL to the command parser register whitelist. | Kenneth Graunke | 1 | -0/+2 |
| 2014-04-02 | drm/i915: Reject commands that would store to global HWS page | Brad Volkin | 1 | -0/+1 |
| 2014-04-02 | drm/i915: Enable PPGTT command parser checks | Brad Volkin | 1 | -0/+6 |
| 2014-04-02 | drm/i915: Reject commands that explicitly generate interrupts | Brad Volkin | 1 | -0/+1 |
| 2014-04-02 | drm/i915: Enable register whitelist checks | Brad Volkin | 1 | -0/+3 |
| 2014-04-02 | drm/i915: Add register whitelist for DRM master | Brad Volkin | 1 | -0/+6 |
