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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2015-04-28drm/i915/chv: Implement WaDisableShadowRegForCpdDeepak S1-0/+2
2015-04-23drm/i915: cope with large i2c transfersDmitry Torokhov1-0/+1
2015-03-25drm/i915: Add fault address to error state for gen8 and gen9Mika Kuoppala1-0/+3
2015-03-20drm/i915: Use down ei for manual Baytrail RPS calculationsChris Wilson1-1/+0
2015-03-20drm/i915: Improved w/a for rps on BaytrailChris Wilson1-2/+2
2015-03-18drm/i915/skl: Added new macrosAkash Goel1-0/+9
2015-03-18drm/i915: Use FW_WM() macro for older gmch platforms tooVille Syrjälä1-2/+2
2015-03-18drm/i915: Add polish to VLV WM shift+mask operationsVille Syrjälä1-5/+5
2015-03-18drm/i915: Disable DDR DVFS on CHVVille Syrjälä1-0/+5
2015-03-18drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä1-0/+3
2015-03-18drm/i915: Program PFI credits for VLVVidya Srinivas1-0/+8
2015-03-18drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä1-2/+2
2015-03-18drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman1-0/+2
2015-03-18drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman1-0/+1
2015-03-18drm/i915: Disable M2 frac division for integer caseVijay Purushothaman1-0/+1
2015-03-18drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee1-0/+11
2015-03-18drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee1-0/+2
2015-03-18drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä1-0/+3
2015-03-18drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä1-1/+4
2015-03-18drm/i915: Hide VLV DDL precision handlingVille Syrjälä1-6/+2
2015-03-18drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä1-4/+0
2015-03-18drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä1-0/+1
2015-03-18drm/i915: Fix trivial typos in comments and warning messageYannick Guerrini1-1/+1
2015-02-24drm/i915: Support for RR switching on VLVVandana Kannan1-0/+1
2015-02-24drm/i915/skl: Tune IZ hashing when subslices are unbalancedDamien Lespiau1-0/+2
2015-02-24drm/i915: Request full SSEU enablement on Gen9Jeff McGee1-0/+13
2015-02-24drm/i915/skl: Add SKL HW status to SSEU statusJeff McGee1-0/+20
2015-02-24drm/i915/skl: Determine SKL slice/subslice/EU infoJeff McGee1-0/+11
2015-02-23drm/i915/skl: Implement WaDisablePowerCompilerClockGatingDamien Lespiau1-2/+3
2015-02-23drm/i915: Add new PHY reg definitions for lock thresholdVijay Purushothaman1-0/+10
2015-02-14drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrementDamien Lespiau1-0/+3
2015-02-14drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChickenDamien Lespiau1-0/+4
2015-02-14drm/i915/skl: Implement WaBarrierPerformanceFixDisableDamien Lespiau1-0/+1
2015-02-14drm/i915/skl: Implement WaCcsTlbPrefetchDisable:sklDamien Lespiau1-0/+1
2015-02-14drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau1-0/+3
2015-02-14drm/i915/skl: Implement WaDisableHDCInvalidationDamien Lespiau1-0/+1
2015-02-14drm/i915/skl: Implement WaDisableLSQCROPERFforOCLDamien Lespiau1-0/+3
2015-02-14drm/i915/skl: Implement WaDisablePartialResolveInVcDamien Lespiau1-0/+1
2015-02-14drm/i915/skl: Implement WaSetGAPSunitClckGateDisableDamien Lespiau1-0/+1
2015-02-14drm/i915: Detect eDRAM with the enabled bit onlyDamien Lespiau1-0/+1
2015-02-14drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherentDamien Lespiau1-2/+3
2015-02-14drm/i915/gen9: Implement WaEnableYV12BugFixInHalfSliceChicken7Nick Hoath1-0/+3
2015-02-14drm/i915/gen9: h/w w/a: syncing dependencies between camera and graphicsNick Hoath1-0/+1
2015-02-14drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M1-0/+20
2015-01-28drm/i915/skl: Enabling PSR on SkylakeSonika Jindal1-0/+5
2015-01-27drm/i915/skl: Gen9 coarse power gatingZhe Wang1-0/+3
2015-01-27drm/i915: New offset for reading frequencies on CHV.Deepak S1-0/+9
2015-01-27drm/i915/chv: Populate total EU count on CherryviewDeepak S1-0/+11
2015-01-13drm/i915: Improve HiZ throughput on Cherryview.Kenneth Graunke1-0/+3
2015-01-13Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter1-3/+18
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