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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2014-04-25drm/i915: Move all ring resets before setting the HWS pageChris Wilson1-0/+1
2014-03-28drm/i915: Broadwell expands ACTHD to 64bitChris Wilson1-0/+1
2014-03-28drm/i915/bdw: Implement Wa4x4STCOptimizationDisable:bdwDamien Lespiau1-1/+2
2014-03-20drm/i915: Enabling 128x128 and 256x256 ARGB Cursor SupportSagar Kamble1-0/+4
2014-03-12drm/i915: wait for rings to become idle once disabledNaresh Kumar Kachhi1-0/+2
2014-03-08drm/i915: Implement command buffer parsing logicBrad Volkin1-0/+12
2014-03-08drm/i915: sanitize PUNIT register macro definitionsImre Deak1-6/+22
2014-03-06drm/i915: Unify CHICKEN_PIPESL_1 register definitionsVille Syrjälä1-8/+2
2014-03-06drm/i915: Implement WaDisableSDEUnitClockGating:bdwVille Syrjälä1-0/+3
2014-03-06drm/i915: Disable semaphore wait event idle message on BDWVille Syrjälä1-0/+3
2014-03-06drm/i915: Add thread stall DOP clock gating workaround on Broadwell.Kenneth Graunke1-0/+1
2014-03-06drm/i915: Add a partial instruction shootdown workaround on Broadwell.Kenneth Graunke1-0/+3
2014-03-06drm/i915: Revert workaround for disabling L3 cache aging on IVBChris Wilson1-1/+1
2014-03-04drm/i915: Change IVB WIZ hashing mode to 16x4Ville Syrjälä1-0/+1
2014-03-04drm/i915: Fix SNB GT_MODE register setupVille Syrjälä1-1/+5
2014-02-13drm/i915: Convert DIP port switch cases to a simple macroVille Syrjälä1-3/+1
2014-02-13drm/i915: Some polish for the new pipestat_irq_handlerDaniel Vetter1-4/+0
2014-02-12drm/i915: Disable display when fused offDamien Lespiau1-0/+2
2014-02-12drm/i915: vlv: handle only enabled pipestat interrupt eventsImre Deak1-0/+4
2014-02-12drm/i915: vlv: fix mapping of pipestat enable to status bitsImre Deak1-0/+3
2014-02-12drm/i915: pass status instead of enable flags to i915_enable_pipestatImre Deak1-0/+3
2014-02-12drm/i915: Consolidate FUSE_STRAP in one set of definesDamien Lespiau1-10/+8
2014-02-12drm/i915: Make the intel_device_info structure kept in dev_priv writableDamien Lespiau1-74/+74
2014-02-12drm/i915: Disable SF pipelined attribute fetch for SNBVille Syrjälä1-1/+2
2014-02-05drm/i915: unify FLIP_DONE macro namesImre Deak1-9/+9
2014-02-05drm/i915: Reorganize display pipe register accessesAntti Koskipaa1-125/+159
2014-02-04drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power...Deepak S1-0/+4
2014-01-30drm/i915: enable HiZ Raw Stall Optimization on HSWChia-I Wu1-0/+2
2014-01-28drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlvVille Syrjälä1-0/+3
2014-01-27drm/i915: GEN7_MSG_CONTROL is ivb-onlyDaniel Vetter1-0/+2
2014-01-26drm/i915: Fix FBC_FENCE_OFFVille Syrjälä1-1/+1
2014-01-26drm/i915: Improve FBC plane defines a bitVille Syrjälä1-5/+3
2014-01-24drm/i915: clock readout support for DDI v3Jesse Barnes1-0/+10
2014-01-24drm/i915: Only restore backlight combination mode reg for umsDaniel Vetter1-1/+2
2014-01-24Revert "drm/i915: Mask reserved bits in display/sprite address registers"Daniel Vetter1-2/+0
2014-01-23drm/i915: VLV2 - Fix hotplug detect bitsTodd Previte1-3/+7
2014-01-22drm/i915: g4x/vlv: fix dp aux interrupt maskImre Deak1-1/+2
2014-01-10drm/i915/vlv: Add drpc debugfs support for valleyviewDeepak S1-0/+2
2013-12-17drm/i915: remove unused WM definesImre Deak1-36/+0
2013-12-17drm/i915: Add IVB DDB partitioning controlVille Syrjälä1-0/+2
2013-12-17drm/i915: Reorder/respace MI instruction definitionBen Widawsky1-26/+26
2013-12-13drm/i915/bdw: Implement ff workaroundsBen Widawsky1-0/+1
2013-12-13drm/i915/bdw: Force all Data Cache Data Port access to be Non-CoherentBen Widawsky1-0/+4
2013-12-12drm/i915: Use FLISDSI interface for band gap resetShobhit Kumar1-0/+1
2013-12-12drm/i915: Record BB_ADDR for every ringVille Syrjälä1-1/+2
2013-12-04drm/i915: Fix bogus FBC1 definesVille Syrjälä1-2/+2
2013-11-28drm/i915/vlv: use parallel context restore when coming out of RC6Jesse Barnes1-0/+1
2013-11-28drm/i915: Fix GT wake FIFO free entries for VLVVille Syrjälä1-1/+2
2013-11-28drm/i915: Report all GTFIFODBG errorsVille Syrjälä1-1/+4
2013-11-21drm/i915: Enable pipe gamma for spritesVille Syrjälä1-1/+1
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