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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2012-08-17drm/i915: fix hsw uncached pteDaniel Vetter1-0/+1
2012-07-20drm/i915: fix up PCH backlight #define mixupDaniel Vetter1-1/+1
2012-07-20drm/i915: Add comments to explain the BSD tail write workaroundChris Wilson1-4/+4
2012-07-20drm/i915/context: Add missing IVB context sizesBen Widawsky1-1/+5
2012-07-20drm/i915/context/: s/CTX/CXTBen Widawsky1-9/+9
2012-07-05drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov1-0/+3
2012-07-05drm/i915: adjust framebuffer base address on gen4+Daniel Vetter1-1/+1
2012-07-05drm/i915: introduce crtc->dspaddr_offsetDaniel Vetter1-0/+1
2012-07-05drm/i915: fix PIPE_DDI_PORT_MASKPaulo Zanoni1-1/+1
2012-07-05drm/i915: enable RC6 workaround on HaswellEugeni Dodonov1-0/+5
2012-07-05drm/i915: add RPS configuration for HaswellEugeni Dodonov1-0/+1
2012-07-04drm/i915: support Haswell force wakingEugeni Dodonov1-0/+1
2012-07-04drm/i915: Implement w/a for sporadic read failures on waking from rc6Chris Wilson1-0/+4
2012-06-28drm/i915: fix PIPE_WM_LINETIME definitionPaulo Zanoni1-1/+1
2012-06-25Merge tag 'v3.5-rc4' into drm-intel-next-queuedDaniel Vetter1-3/+40
2012-06-21drm/i915: enable display messages to GT on ValleyViewJesse Barnes1-2/+2
2012-06-20drm/i915: add HDMI and DP port enumeration on ValleyViewJesse Barnes1-1/+0
2012-06-20drm/i915: Enable DP panel power sequencing for ValleyViewShobhit Kumar1-0/+13
2012-06-20drm/i915: ValleyView mode setting limits and PLL functionsJesse Barnes1-0/+1
2012-06-18drm/i915: add L3 bank clock gating disable on VLVJesse Barnes1-0/+3
2012-06-18drm/i915: add TDL unit clock gating disable for VLVJesse Barnes1-0/+1
2012-06-18drm/i915: disable RCBP and VDS unit clock gating on SNB and VLVJesse Barnes1-0/+1
2012-06-14drm/i915: PIPE_CONTROL_TLB_INVALIDATEBen Widawsky1-0/+1
2012-06-14drm/i915: Ivybridge MI_ARB_ON_OFF context w/aBen Widawsky1-0/+3
2012-06-14drm/i915: CXT_SIZE register offsets addedBen Widawsky1-0/+21
2012-06-12drm/i915: clear up backlight #define confusion on gen4+Daniel Vetter1-20/+35
2012-06-12drm/i915: pnv has a backlight polarity control bit, tooDaniel Vetter1-0/+2
2012-06-07drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handlerAdam Jackson1-3/+32
2012-06-05drm/i915: fix up ivb plane 3 pageflipsDaniel Vetter1-0/+8
2012-05-31drm/i915: remap l3 on hw initBen Widawsky1-0/+3
2012-05-31drm/i915: Dynamic Parity Detection handlingBen Widawsky1-0/+17
2012-05-31drm/i915: explicitly disable the DIPs we're not usingPaulo Zanoni1-0/+6
2012-05-21drm/i915: SDVO hotplug have different interrupt status bits for i915/i965/g4xChris Wilson1-3/+8
2012-05-21drm/i915: Inspect the right status bits for DP/HDMI hotplug on gen4Chris Wilson1-6/+15
2012-05-20drm/i915: implement hsw_write_infoframePaulo Zanoni1-0/+4
2012-05-20drm/i915: add new Haswell DIP controls registersEugeni Dodonov1-0/+36
2012-05-08drm/i915: set the DIP port on ibx_write_infoframePaulo Zanoni1-0/+1
2012-05-08drm/i915: mask the video DIP frequency when changing itPaulo Zanoni1-0/+1
2012-05-08drm/i915: mask the video DIP port selectPaulo Zanoni1-0/+1
2012-05-08drm/i915: DSL_LINEMASK is 12 bits only on gen2Paulo Zanoni1-1/+2
2012-05-06drm/i915: Support pageflipping interrupts for all 3-pipes on IVBChris Wilson1-2/+5
2012-05-05drm/i915: also reset the media engine on gen4/5Daniel Vetter1-0/+1
2012-05-03drm/i915: use the new masked bit macro some moreDaniel Vetter1-2/+0
2012-05-03drm/i915: create macros to handle masked bitsDaniel Vetter1-5/+3
2012-05-03drm/i915: manage PCH PLLs separately from pipesJesse Barnes1-3/+3
2012-04-18drm/i915: [GEN7] Use HW scheduler for fixed function shadersBen Widawsky1-0/+15
2012-04-18drm/i915: Replace open coded MI_BATCH_GTTChris Wilson1-0/+1
2012-04-17drm/i915: Mask reserved bits in display/sprite address registersArmin Reese1-0/+7
2012-04-17drm/i915: add WRPLL divider programming bitsEugeni Dodonov1-0/+4
2012-04-17drm/i915: add definition of LPT FDI port width registersEugeni Dodonov1-0/+3
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