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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2013-08-07drm/i915: fix gen4 digital port hotplug definitionsDaniel Vetter1-3/+9
2013-07-01drm/i915: Fix context sizes on HSWBen Widawsky1-8/+7
2013-07-01drm/i915: Fix VLV sprite register offsetsVille Syrjälä1-25/+25
2013-07-01drm/i915: s/LFP/LPF in DPIO PLL register namesVille Syrjälä1-3/+3
2013-07-01drm/i915: Fix up sdvo hpd pins for i965g/gmDaniel Vetter1-7/+6
2013-06-18drm/i915: explicitly set up PIPECONF (and gamma table) on haswellDaniel Vetter1-3/+3
2013-06-13drm/i915: Try harder to disable trickle feed on VLVVille Syrjälä1-0/+2
2013-06-10drm/i915: scrap register address storageDaniel Vetter1-3/+3
2013-06-10drm/i915: refactor PCH_DPLL_SEL #definesDaniel Vetter1-9/+3
2013-06-07drm/i915: WA: FBC Render Nuke.Rodrigo Vivi1-0/+4
2013-06-06Revert "drm/i915: Include display_mmio_offset in sequencer index/data registers"Ville Syrjälä1-8/+2
2013-06-05drm/i915: Fix DSPCLK_GATE_D for VLVVille Syrjälä1-1/+1
2013-05-31drm/i915: implement IPS featurePaulo Zanoni1-0/+11
2013-05-31drm/i915: Enable vebox interruptsBen Widawsky1-0/+3
2013-05-31drm/i915: consolidate interrupt naming schemeBen Widawsky1-58/+43
2013-05-31drm/i915: make PM interrupt writes non-destructiveBen Widawsky1-1/+1
2013-05-31drm/i915: properly set HSW WM_LP watermarksPaulo Zanoni1-0/+4
2013-05-31drm/i915: properly set HSW WM_PIPE registersPaulo Zanoni1-0/+3
2013-05-31drm/i915: Vebox ringbuffer initBen Widawsky1-0/+1
2013-05-31drm/i915: Add VECS semaphore bitsBen Widawsky1-13/+27
2013-05-31drm/i915: Semaphore MBOX update generalizationBen Widawsky1-0/+1
2013-05-31drm/i915: Comments for semaphore clarificationBen Widawsky1-6/+6
2013-05-24drm/i915: refactor VLV IOSF sideband accessors to use one helperJani Nikula1-50/+43
2013-05-23drm/i915: set FORCE_ARB_IDLE_PLANES workaroundPaulo Zanoni1-0/+3
2013-05-21Merge tag 'v3.10-rc2' into drm-intel-next-queuedDaniel Vetter1-7/+4
2013-05-10drm/i915: HSW FBC WaFbcDisableDpfcClockGatingRodrigo Vivi1-0/+3
2013-05-10drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueueRodrigo Vivi1-0/+7
2013-05-10drm/i915: Add support for FBC on Ivybridge.Rodrigo Vivi1-0/+6
2013-05-10drm/i915: BIOS and power context stolen mem handling for VLV v7Jesse Barnes1-0/+1
2013-05-07Revert "drm/i915: Calculate correct stolen size for GEN7+"Ben Widawsky1-2/+0
2013-05-06drm/i915: Apply OCD to data/link m/n register #definesDaniel Vetter1-37/+37
2013-05-06drm/i915: PCH_ prefix for transcoder timingsDaniel Vetter1-35/+35
2013-05-06drm/i915: s/TRANSCONF/PCH_TRANSCONF/Daniel Vetter1-3/+4
2013-05-02drm/i915: simplify DP/DDI port width macrosDaniel Vetter1-9/+2
2013-04-30drm/i915: hw state readout support for pipe timingsDaniel Vetter1-0/+1
2013-04-29drm/i915: hw state readout support for fdi m/nDaniel Vetter1-0/+1
2013-04-29drm/i915: hw state readout support for pipe_config->fdi_lanesDaniel Vetter1-8/+3
2013-04-25drm/i915: hsw backlight registers need transcoder instead of pipeJani Nikula1-0/+4
2013-04-24drm/i915: Make data/link N value power of twoVille Syrjälä1-8/+4
2013-04-19drm/i915: Move the CSC_MODE bits next to the registerVille Syrjälä1-4/+3
2013-04-19drm/i915: print Gen5+ CPU/PCH poison interruptsPaulo Zanoni1-0/+2
2013-04-19drm/i915: report Gen5+ CPU and PCH FIFO underrunsPaulo Zanoni1-2/+11
2013-04-19drm/i915: magic VLV PLL registers in the dpio sidebandDaniel Vetter1-2/+116
2013-04-18drm/i915: turbo & RC6 support for VLV v7Jesse Barnes1-0/+21
2013-04-18drm/i915: preserve the PBC bits of TRANS_CHICKEN2Paulo Zanoni1-2/+5
2013-04-18drm/i915: set CPT FDI RX polarity bits based on VBTPaulo Zanoni1-1/+1
2013-04-18drm/i915: Scale ring, rather than ia, frequency on HaswellChris Wilson1-0/+4
2013-04-18drm/i915: Increase max fence pitch limit to 256KB on IVB+Ville Syrjälä1-0/+1
2013-04-18drm/i915: Configure GAM_ECOCHK appropriatly for Gen7Ville Syrjälä1-0/+5
2013-04-18drm/i915: Add ECOBITS_SNB_BITVille Syrjälä1-0/+1
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