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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2011-03-16Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-nextDave Airlie1-0/+10
2011-03-11drm/i915: Revive combination mode for backlight controlTakashi Iwai1-0/+10
2011-03-07Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+2
2011-03-06drm/i915: Do not overflow the MMADDR write FIFOChris Wilson1-0/+2
2011-03-01drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"Chris Wilson1-1/+4
2011-02-22Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-10/+0
2011-02-22drm/i915: Add support for limited color range of broadcast outputsChris Wilson1-0/+1
2011-02-22drm/i915: Do not handle backlight combination mode speciallyIndan Zupancic1-10/+0
2011-02-16Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-1/+3
2011-02-11drm/i915: disable PCH ports if needed when disabling a CRTCJesse Barnes1-0/+15
2011-02-08drm/i915: cleanup per-pipe reg usageJesse Barnes1-201/+231
2011-02-07drm/i915: Set the transcoder port to none when disabling DP.Eric Anholt1-0/+1
2011-02-02drm/i915: Invalidate TLB caches on SNB BLT/BSD ringsChris Wilson1-1/+3
2011-01-20Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+6
2011-01-19drm/i915: Honour LVDS sync polarity from EDIDBryan Freed1-0/+4
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes1-2/+15
2011-01-19drm/i915: set phase sync pointer override enable before setting phase sync po...Jesse Barnes1-1/+2
2011-01-19drm/i915: add PCH DPLL enable/disable functionsJesse Barnes1-0/+1
2011-01-19drm/i915: add pipe/plane enable/disable functionsJesse Barnes1-2/+3
2011-01-18drm/i915: make the blitter report buffer modifications to the FBC unitJesse Barnes1-0/+4
2011-01-18drm/i915: set more FBC chicken bitsJesse Barnes1-0/+2
2011-01-11drm/i915: detect & report PCH display error interruptsJesse Barnes1-0/+29
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes1-3/+47
2011-01-11drm/i915: Mask USER interrupts on gen6 (until required)Chris Wilson1-0/+1
2011-01-11drm/i915: support low power watermarks on IronlakeJesse Barnes1-0/+5
2011-01-11drm/i915: support overclocking on Sandy BridgeJesse Barnes1-0/+1
2011-01-11drm/i915: fix calculation of eDP signal levels on SandybridgeYuanhan Liu1-4/+5
2011-01-05Merge branch 'master' of /home/airlied/kernel/linux-2.6 into drm-core-nextDave Airlie1-0/+10
2010-12-23drm/i915: Verify Ironlake eDP presence on DP_A using the capability fuseChris Wilson1-0/+7
2010-12-23drm/i915: Set the required VFMUNIT clock gating disable on Ironlake.Eric Anholt1-0/+3
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes1-1/+7
2010-12-17drm/i915: Add support for precise vblank timestamping (v2)Mario Kleiner1-0/+1
2010-12-15drm/i915: Add frame buffer compression on SandybridgeYuanhan Liu1-0/+10
2010-12-15drm/i915: Add self-refresh support on SandybridgeYuanhan Liu1-0/+40
2010-12-09drm/i915: Enable RC6 autodownclocking on SandybridgeChris Wilson1-0/+59
2010-12-09drm/i915: Terminate the FORCE WAKE after we have finished readingChris Wilson1-0/+1
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson1-1/+18
2010-12-05drm/i915: Enable CB tuning of the Display PLLChris Wilson1-0/+1
2010-12-03Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+1
2010-12-03drm/i915: Always set the DP transcoder config to 8BPC.Eric Anholt1-0/+1
2010-11-25drm/i915: Add a mechanism for pipelining fence register updatesDaniel Vetter1-1/+7
2010-11-22drm/i915: Add support for GPU reset on gen6.Eric Anholt1-0/+6
2010-11-22drm/i915: Capture interesting display registers on errorChris Wilson1-1/+5
2010-11-11drm/i915: Remove the definitions for Primary Ring BufferChris Wilson1-4/+6
2010-11-11drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring registerZou Nan hai1-0/+1
2010-11-08drm/i915: Apply display workaround required according to the B-Spec.Eric Anholt1-0/+2
2010-11-08drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.Eric Anholt1-0/+13
2010-10-30drm/i915: Record BSD engine error stateChris Wilson1-0/+4
2010-10-29drm/i915: Record BLT engine error stateChris Wilson1-0/+4
2010-10-28drm/i915: Capture ERROR register on Sandybridge hangsChris Wilson1-0/+2
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