summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_gem_tiling.c
AgeCommit message (Expand)AuthorFilesLines
2009-09-08drm/i915: get the bridge device once.Dave Airlie1-45/+20
2009-09-05drm/i915: fix tiling on IGDNGZhenyu Wang1-8/+7
2009-07-11drm/i915: Zap the GTT mapping when transitioning from untiled to tiled.Eric Anholt1-0/+6
2009-06-19drm/i915: check for CONFIG_PNP before using pnp functionKeith Packard1-0/+2
2009-06-18drm/i915: Clear fence register on tiling stride change.Chris Wilson1-16/+51
2009-06-09drm/i915: enable MCHBAR if neededJesse Barnes1-0/+145
2009-06-05drm/i915: Disable tiling on IGDNG for nowZhenyu Wang1-0/+7
2009-05-27drm/i915: Fix tiling pitch handling on 8xx.Eric Anholt1-3/+11
2009-04-18drm/i915: fix transition to I915_TILING_NONEKeith Packard1-1/+0
2009-04-08drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU.Eric Anholt1-2/+109
2009-04-01drm/i915: fix up tiling/fence reg setup on i8xx class hwDaniel Vetter1-0/+16
2009-03-28drm/i915: Change DCC tiling detection case to cover only mobile parts.Eric Anholt1-16/+15
2009-02-20drm/i915: hold mutex for unreference() in i915_gem_tiling.cChris Wilson1-4/+2
2009-02-08drm/i915: Unref the object after failing to set tiling mode.Chris Wilson1-1/+4
2009-02-08drm/i915: add fence register management to execbufJesse Barnes1-1/+87
2008-12-29drm/i915: add GEM GTT mapping supportJesse Barnes1-0/+1
2008-12-04drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling.Eric Anholt1-3/+4
2008-10-18i915: GM45 has GM965-style MCH setup.Eric Anholt1-2/+3
2008-10-18drm: G33-class hardware has a newer 965-style MCH (no DCC register).Eric Anholt1-1/+1
2008-10-18drm: Add GEM ("graphics execution manager") to i915 driver.Eric Anholt1-0/+256
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-03 14:38:48 +0300