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path: root/drivers/gpu/drm/i915/display
AgeCommit message (Expand)AuthorFilesLines
2025-04-14drm/i915: don't capture DERRMR for VLV/CHVJani Nikula1-1/+1
2025-04-14drm/i915: use display snapshot mechanism for display irq regsJani Nikula3-0/+38
2025-04-14drm/i915/dpio: have chv_data_lane_soft_reset() get/put dpio internallyJani Nikula3-20/+16
2025-04-14drm/i915/vrr: Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwardsJouni Högander1-1/+4
2025-04-12drm/i915/pch: clean up includesJani Nikula1-1/+3
2025-04-12drm/i915/pch: move PCH detection to intel_display_driver_early_probe()Jani Nikula3-2/+5
2025-04-12drm/i915/display: Convert intel_pch towards intel_displayRodrigo Vivi3-135/+153
2025-04-12drm/{i915,xe}: Move intel_pch under displayRodrigo Vivi2-0/+372
2025-04-11drm/i915/backlight: Modify condition to use panel luminanceSuraj Kandpal1-1/+2
2025-04-11drm/i915/debugfs: move PCH type to display capsJani Nikula1-0/+3
2025-04-11drm/i915/debugfs: remove i915_display_capabilitiesJani Nikula1-12/+0
2025-04-10drm/i915: Simplify combo PLL frac w/aVille Syrjälä1-5/+2
2025-04-10drm/i915: Apply the combo PLL frac w/a on DG1Ville Syrjälä1-0/+1
2025-04-09drm/i915/wm: convert i9xx_wm.c internally to struct intel_displayJani Nikula1-425/+397
2025-04-09drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interfaceJani Nikula1-187/+196
2025-04-09drm/i915/wm: convert i9xx_wm.h external interfaces to struct intel_displayJani Nikula5-32/+37
2025-04-09drm/i915/wm: convert skl_watermarks.c internally to struct intel_displayJani Nikula1-286/+250
2025-04-09drm/i915/wm: convert skl_watermark.h external interfaces to struct intel_displayJani Nikula8-90/+88
2025-04-09drm/i915/wm: convert intel_wm.c internally to struct intel_displayJani Nikula1-61/+61
2025-04-09drm/i915/wm: convert intel_wm.h external interfaces to struct intel_displayJani Nikula9-68/+80
2025-04-09drm/i915/dsi: unify naming and simplify checks for dphy paramsJani Nikula1-60/+22
2025-04-09drm/i915/dsi: separate clock and data lane prepare timingJani Nikula1-8/+8
2025-04-09drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changedAnkit Nautiyal1-1/+3
2025-04-07drm/i915/dp_mst: Rename intel_dp::mst.active_links to mst.active_streamsImre Deak2-7/+7
2025-04-07drm/i915/dp_mst: Use intel_dp_mst_active_streams() instead of open-coding itImre Deak3-6/+7
2025-04-07drm/i915/dp_mst: Rename intel_dp_mst_encoder_active_links() to intel_dp_mst_a...Imre Deak4-21/+20
2025-04-07drm/i915/dp_mst: Remove stream count assert from intel_dp_check_mst_status()Imre Deak1-2/+0
2025-04-07drm/i915/dp_mst: Add intel_dp_mst_{inc, dec}_active_streams()Imre Deak1-16/+27
2025-04-07drm/i915/dp: Rename intel_dp::link_trained to link.activeImre Deak6-12/+12
2025-04-07drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changedAnkit Nautiyal1-1/+3
2025-04-07drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECCVivek Kasireddy1-1/+13
2025-04-07drm/i915/dp: Reject HBR3 when sink doesn't support TPS4Ville Syrjälä1-7/+42
2025-04-07drm/i915: Fix scanline_offset for LNL+ and BMG+Ville Syrjälä1-1/+3
2025-04-04drm/i915: Eliminate intel_compute_sagv_mask()Ville Syrjälä1-40/+24
2025-04-04drm/i915: Skip bw stuff if per-crtc sagv state doesn't changeVille Syrjälä2-3/+16
2025-04-04drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check()Ville Syrjälä3-11/+10
2025-04-04drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.cVille Syrjälä3-7/+8
2025-04-04drm/i915: Extract intel_bw_check_sagv_mask()Ville Syrjälä4-27/+46
2025-04-04drm/i915: Extract intel_bw_modeset_checks()Ville Syrjälä4-9/+36
2025-04-04drm/i915: Drop force_check_qgvVille Syrjälä2-12/+6
2025-04-04drm/i915: Flag even inactive crtcs as "inherited"Ville Syrjälä2-11/+14
2025-04-04drm/i915: Do more bw readoutVille Syrjälä2-0/+7
2025-04-04drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changesVille Syrjälä1-4/+13
2025-04-04drm/i915: Pass intel_dbuf_bw to skl_*_calc_dbuf_bw() explicitlyVille Syrjälä1-7/+6
2025-04-04drm/i915: Extract intel_dbuf_bw_changed()Ville Syrjälä1-6/+17
2025-04-04drm/i915: s/intel_crtc_bw/intel_dbuf_bw/Ville Syrjälä1-12/+12
2025-04-04drm/i915: Drop the cached per-pipe min_cdclk[] from bw stateVille Syrjälä2-10/+8
2025-04-02drm/i915/dp: Reject HBR3 when sink doesn't support TPS4Ville Syrjälä1-7/+42
2025-04-02drm/i915/psr: Prevent DP Panel Replay as well when CRC is enableJouni Högander1-6/+6
2025-04-02drm/i915: Eliminate the initial_plane_phys_{smem,lmem}() duplicationVille Syrjälä1-73/+2
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 10:41:05 +0300