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path: root/drivers/gpu/drm/i915/display/intel_vrr.c
AgeCommit message (Expand)AuthorFilesLines
2025-06-11drm/i915/display: drop i915_reg.h include where possibleJani Nikula1-1/+0
2025-06-09drm/i915: split out display register macros to a separate fileJani Nikula1-0/+1
2025-05-19drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDPAnkit Nautiyal1-0/+23
2025-04-14drm/i915/vrr: Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwardsJouni Högander1-1/+4
2025-04-01drm/i915: reduce intel_wakeref.h dependenciesJani Nikula1-0/+2
2025-03-31drm/i915/display: Avoid use of VTOTAL.Vtotal bitsAnkit Nautiyal1-0/+10
2025-03-25drm/i915/vrr: Set trans_vrr_ctl in intel_vrr_set_transcoder_timings()Ankit Nautiyal1-0/+4
2025-03-25drm/i915/vrr: Always use VRR timing generator for PTL+Ankit Nautiyal1-1/+3
2025-03-25drm/i915/vrr: Allow fixed_rr with pipe joinerAnkit Nautiyal1-7/+11
2025-03-25drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset blockAnkit Nautiyal1-1/+0
2025-03-25drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr()Ankit Nautiyal1-1/+0
2025-03-25drm/i915/vrr: Use fixed timings for platforms that support VRRAnkit Nautiyal1-4/+4
2025-03-25drm/i915/display: Use fixed_rr timings in modeset sequenceAnkit Nautiyal1-8/+43
2025-03-25drm/i915/vrr: Set vrr.enable for VRR TG with fixed_rrAnkit Nautiyal1-1/+7
2025-03-25drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable}Ankit Nautiyal1-13/+27
2025-03-25drm/i915/vrr: Refactor condition for computing vmax and LRRAnkit Nautiyal1-6/+8
2025-03-25drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rrAnkit Nautiyal1-0/+2
2025-03-24drm/i915/vrr: Avoid reading vrr.enable based on fixed_rr checkAnkit Nautiyal1-2/+1
2025-03-24drm/i915/display: Add fixed_rr to crtc_state dumpAnkit Nautiyal1-1/+0
2025-03-13drm/i915/vrr: Prepare for fixed refresh rate timingsAnkit Nautiyal1-5/+82
2025-03-13drm/i915/vrr: Use crtc_vtotal for vminAnkit Nautiyal1-11/+10
2025-03-13drm/i915/vrr: Track vrr.enable only for variable timingAnkit Nautiyal1-2/+16
2025-03-13drm/i915/vrr: Disable CMRRAnkit Nautiyal1-1/+2
2025-03-13drm/i915/vrr: Make helpers for cmrr and vrr timingsAnkit Nautiyal1-17/+28
2025-03-13drm/i915:vrr: Separate out functions to compute vmin and vmaxAnkit Nautiyal1-8/+30
2025-03-13drm/i915/vrr: Remove unwanted commentAnkit Nautiyal1-5/+0
2025-02-12drm/i915/vrr: Check that the push send bit is clear after delayed vblankVille Syrjälä1-0/+34
2025-01-30drm/i915/vrr: Compute vrr.vsync_{start, end} during full modesetMitul Golani1-15/+10
2025-01-15drm/i915/vrr: Plumb the DSB into intel_vrr_send_push()Ville Syrjälä1-3/+11
2025-01-15drm/i915/vrr: Add extra vblank delay to estimatesVille Syrjälä1-6/+27
2025-01-15drm/i915/vrr: Fix vmin/vmax/flipline on TGL when using vblank delayVille Syrjälä1-6/+26
2025-01-15drm/i915/vrr: Drop the extra vmin adjustment for ADL+Ville Syrjälä1-11/+26
2025-01-15drm/i915/vrr: Introduce intel_vrr_vblank_delay()Ville Syrjälä1-0/+6
2025-01-15drm/i915: Introduce intel_vrr_{vmin,vmax}_vtotal()Ville Syrjälä1-0/+11
2025-01-15drm/i915: Fix include orderVille Syrjälä1-1/+1
2024-12-18drm/i915/display: drop unnecessary i915_drv.h includesJani Nikula1-1/+0
2024-11-12drm/i915/display: make CHICKEN_TRANS() display version awareJani Nikula1-1/+1
2024-10-16drm/i915/vrr: Split vrr-compute-config in two phasesAnimesh Manna1-4/+9
2024-10-16drm/i915/vrr: Add helper to check if vrr possibleMitul Golani1-1/+6
2024-08-23drm/i915/vrr: convert to struct intel_displayJani Nikula1-66/+61
2024-07-09drm/i915/display: Cache adpative sync caps to use it laterMitul Golani1-2/+1
2024-06-24drm/i915/display: Consider adjusted_pixel_rate to be u64Mitul Golani1-1/+1
2024-06-17drm/i915/display: Update calculation to avoid overflowMitul Golani1-4/+5
2024-06-13drm/i915/display: Send vrr vsync params whne vrr is enabledMitul Golani1-1/+2
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy1-1/+1
2024-06-11drm/i915: Compute CMRR and calculate vtotalMitul Golani1-11/+81
2024-06-11drm/i915/display: Compute vrr vsync paramsMitul Golani1-8/+9
2024-06-11drm/i915: Update trans_vrr_ctl flag when cmrr is computedMitul Golani1-2/+8
2024-06-11drm/i915: Define and compute Transcoder CMRR registersMitul Golani1-0/+20
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani1-0/+1
generated by cgit v1.2.3 (git 2.39.0) at 2025-11-02 06:16:45 +0300