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path: root/drivers/gpu/drm/i915/display/intel_panel.c
AgeCommit message (Expand)AuthorFilesLines
2025-06-26drm/i915/panel: register drm_panel and call prepare/unprepare for eDPArun R Murthy1-1/+2
2025-06-23drm/i915/panel: make panel funcs staticJani Nikula1-1/+1
2025-06-11drm/i915/panel: sync panel prepared state at registerJani Nikula1-0/+41
2025-06-11drm/i915/panel: register drm_panel and call prepare/unprepare for ICL+ DSIJani Nikula1-1/+81
2025-06-11drm/i915/panel: add panel register/unregisterJani Nikula1-0/+10
2025-03-03drm/i915: relocate intel_plane_ggtt_offset() to intel_atomic_plane.cJani Nikula1-0/+1
2024-12-18drm/i915/display: drop unnecessary i915_drv.h includesJani Nikula1-1/+0
2024-12-09drm/i915/display: convert intel_display_driver.[ch] to struct intel_displayJani Nikula1-2/+1
2024-11-12drm/i915/display: convert display device identification to struct intel_displayJani Nikula1-1/+2
2024-10-23drm/i915/pfit: Extract intel_pfit.cVille Syrjälä1-544/+2
2024-10-23drm/i915/panel: Convert panel code to intel_displayVille Syrjälä1-24/+20
2024-10-23drm/i915/pfit: Check pfit destination window on ILK-BDWVille Syrjälä1-0/+55
2024-10-23drm/i915/pfit: Reject cloning when using pfit on ILK-BDWVille Syrjälä1-0/+27
2024-10-23drm/i915/pfit: Check pfit minimum timings in pre-SKLVille Syrjälä1-1/+58
2024-10-23drm/i915/pfit: Reject pfit downscaling for GMCH platformsVille Syrjälä1-0/+20
2024-10-23drm/i915/pfit: Check pfit scaling factors on ILK-BDWVille Syrjälä1-0/+39
2024-10-23drm/i915/pfit: Check pipe source size against pfit limits on ILK-BDWVille Syrjälä1-1/+51
2024-05-08drm/i915/bios: Get rid of "LVDS" from all LFP data stuffVille Syrjälä1-1/+1
2024-04-18drm/i915/quirks: convert struct drm_i915_private to struct intel_displayJani Nikula1-4/+6
2024-01-08drm/i915: Disable hotplug detection handlers during driver init/shutdownImre Deak1-0/+4
2023-10-26drm/i915/display: Move panel_use_ssc module parameter under displayJouni Högander1-2/+2
2023-10-04drm/i915: convert INTEL_DISPLAY_ENABLED() into a functionJani Nikula1-1/+1
2023-09-20drm/i915: Relocate is_in_vrr_range()Ville Syrjälä1-13/+4
2023-04-20drm/i915: Namespace pfit registers properlyVille Syrjälä1-12/+13
2023-04-20drm/i915: Use REG_BIT() & co for the pre-ilk pfit registersVille Syrjälä1-4/+4
2023-04-13drm/i915: Allow arbitrary refresh rates with VRR eDP panelsVille Syrjälä1-14/+66
2023-01-31drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä1-0/+1
2023-01-26drm/i915/panel: move panel fixed EDID to struct intel_panelJani Nikula1-1/+9
2022-12-09drm/i915: Try to use the correct power sequencer intiially on bxt/glkVille Syrjälä1-0/+1
2022-12-09drm/i915: Do panel VBT init early if the VBT declares an explicit panel typeVille Syrjälä1-0/+1
2022-12-09drm/i915: Introduce intel_panel_init_alloc()Ville Syrjälä1-0/+7
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-10-21drm/i915: Allow panel fixed modes to have differing sync polaritiesVille Syrjälä1-3/+4
2022-10-04drm/i915: Setup final panel drrs_type already during initVille Syrjälä1-3/+3
2022-10-04drm/i915: Tighten DRRS capability reportingVille Syrjälä1-2/+17
2022-09-28drm/i915: Simplify intel_panel_add_edid_alt_fixed_modes()Ville Syrjälä1-2/+2
2022-09-08drm/i915: Add intel_panel_highest_mode()Ville Syrjälä1-0/+15
2022-08-31drm/i915: Allow more varied alternate fixed modes for panelsVille Syrjälä1-19/+6
2022-08-31drm/i915/quirks: abstract checking for display quirksJani Nikula1-2/+3
2022-08-31drm/i915: move vbt to display.vbtJani Nikula1-1/+1
2022-06-01drm/i915: Accept more fixed modes with VRR panelsVille Syrjälä1-12/+37
2022-06-01drm/i915: Print out rejected fixed modesVille Syrjälä1-0/+4
2022-05-27drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä1-7/+6
2022-05-05drm/i915: Respect VBT seamless DRRS min refresh rateVille Syrjälä1-3/+7
2022-03-31drm/i915: Allow higher refresh rate alternate fixed modesVille Syrjälä1-11/+11
2022-03-31drm/i915: Allow an arbitrary number of downclock modesVille Syrjälä1-30/+12
2022-03-31drm/i915: Stop duplicating the EDID fixed/downclock modesVille Syrjälä1-33/+29
2022-03-31drm/i915: Combine the EDID fixed_mode+downclock_mode lookup into oneVille Syrjälä1-2/+9
2022-03-31drm/i915: Nuke intel_drrs_init()Ville Syrjälä1-0/+6
2022-03-31drm/i915: Refactor non-EDID fixed mode duplicationVille Syrjälä1-36/+30
generated by cgit v1.2.3 (git 2.39.0) at 2025-11-02 19:16:04 +0300