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path: root/drivers/gpu/drm/i915/display/intel_drrs.c
AgeCommit message (Expand)AuthorFilesLines
2022-05-27drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä1-3/+0
2022-03-31drm/i915: Move intel_drrs_compute_config() into intel_dp.cVille Syrjälä1-54/+0
2022-03-31drm/i915: Nuke intel_drrs_init()Ville Syrjälä1-24/+0
2022-03-31drm/i915: Put fixed modes directly onto the panel's fixed_modes listVille Syrjälä1-17/+5
2022-03-31drm/i915: Extract intel_edp_has_drrs()Ville Syrjälä1-24/+0
2022-03-22drm/i915: s/enable/active/ for DRRSVille Syrjälä1-10/+12
2022-03-16drm/i915: Deal with bigjoiner vs. DRRSVille Syrjälä1-1/+15
2022-03-16drm/i915: Do DRRS disable/enable during pre/post_plane_update()Ville Syrjälä1-36/+4
2022-03-16drm/i915: Schedule DRRS work from intel_drrs_enable()Ville Syrjälä1-2/+8
2022-03-16drm/i915: Don't cancel/schedule drrs work if the pipe wasn't affectedVille Syrjälä1-9/+8
2022-03-16drm/i915: Determine DRRS frontbuffer_bits ahead of timeVille Syrjälä1-1/+10
2022-03-16drm/i915: Fix DRRS frontbuffer_bits handlingVille Syrjälä1-2/+4
2022-03-16drm/i915: Put the downclock_mode check back into can_enable_drrs()Ville Syrjälä1-3/+5
2022-03-15drm/i915: Implement static DRRSVille Syrjälä1-1/+1
2022-03-15drm/i915: Enable eDP DRRS on ilk/snb port AVille Syrjälä1-4/+4
2022-03-15drm/i915: Stash DRRS state under intel_crtcVille Syrjälä1-153/+100
2022-03-15drm/i915: Eliminate the intel_dp dependency from DRRSVille Syrjälä1-48/+32
2022-03-15drm/i915: Introduce intel_drrs_type_str()Ville Syrjälä1-2/+17
2022-03-15drm/i915: Introduce intel_panel_drrs_type()Ville Syrjälä1-7/+3
2022-03-15drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä1-4/+7
2022-03-15drm/i915: Nuke dev_priv->drrs.typeVille Syrjälä1-6/+4
2022-03-10drm/i915: Rename PIPECONF refresh select bitsVille Syrjälä1-2/+2
2022-03-10drm/i915: Clean up DRRS refresh rate enumVille Syrjälä1-24/+20
2022-03-10drm/i915: Polish drrs type enumVille Syrjälä1-5/+5
2022-03-10drm/i915: Program MSA timing delay on ilk/snb/ivbVille Syrjälä1-0/+3
2022-03-10drm/i915: Pimp DRRS debugsVille Syrjälä1-5/+13
2022-03-10drm/i915: Constify intel_drrs_init() argsVille Syrjälä1-1/+1
2022-03-10drm/i915: Fix up some DRRS type checksVille Syrjälä1-2/+2
2022-02-01drm/i915: Clear DP M2/N2 when not doing DRRSVille Syrjälä1-1/+5
2022-02-01drm/i915: Extract can_enable_drrs()Ville Syrjälä1-12/+19
2022-02-01drm/i915: Disable DRRS on IVB/HSW port != AVille Syrjälä1-0/+8
2022-02-01drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä1-1/+4
2022-02-01drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä1-3/+2
2022-02-01drm/i915: Nuke intel_dp_set_m_n()Ville Syrjälä1-2/+3
2022-01-28drm/i915: Move drrs hardware bit frobbing to small helpersVille Syrjälä1-31/+36
2022-01-28drm/i915: s/gmch_{m,n}/data_{m,n}/Ville Syrjälä1-1/+1
2021-09-08drm/i915/display: Prepare DRRS for frontbuffer rendering dropJosé Roberto de Souza1-0/+9
2021-09-08drm/i915/display: Share code between intel_drrs_flush and intel_drrs_invalidateJosé Roberto de Souza1-50/+32
2021-09-08drm/i915/display: Some code improvements and code style fixes for DRRSJosé Roberto de Souza1-38/+20
2021-08-30drm/i915/display: Renaming DRRS functions to intel_drrs_*()José Roberto de Souza1-58/+45
2021-08-30drm/i915/display: Move DRRS code its own fileJosé Roberto de Souza1-0/+477
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