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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)AuthorFilesLines
2025-08-01drm/i915/dpll: use intel_de_wait_custom() instead of wait_for_us()Jani Nikula1-6/+14
2025-06-11drm/i915/display: drop i915_reg.h include where possibleJani Nikula1-1/+0
2025-06-09drm/i915: split out display register macros to a separate fileJani Nikula1-0/+1
2025-05-20drm/i915/dpll: Rename intel_update_active_dpllSuraj Kandpal1-2/+2
2025-05-20drm/i915/dpll: Rename intel_compute_dpllSuraj Kandpal1-4/+4
2025-05-20drm/i915/dpll: Rename intel_<release/reserve>_dpllSuraj Kandpal1-13/+13
2025-05-20drm/i915/dpll: Rename intel_reference_dpll_crtcSuraj Kandpal1-6/+6
2025-05-20drm/i915/dpll: Rename intel_unreference_dpll_crtcSuraj Kandpal1-5/+5
2025-05-20drm/i915/dpll: Rename intel_[enable/disable]_dpllSuraj Kandpal1-4/+4
2025-05-20drm/i915/dpll: Move away from using shared dpllSuraj Kandpal1-118/+117
2025-05-20drm/i915/dpll: Rename intel_shared_dpllSuraj Kandpal1-114/+114
2025-05-20drm/i915/dpll: Rename intel_shared_dpll_funcsSuraj Kandpal1-12/+12
2025-05-20drm/i915/dpll: Rename macro for_each_shared_dpllSuraj Kandpal1-8/+8
2025-05-20drm/i915/dpll: Rename intel_shared_dpll_stateSuraj Kandpal1-28/+28
2025-04-22drm/i915/display: drop lots of unnecessary #include i915_drv.hJani Nikula1-1/+4
2025-04-22drm/i915/display: pass struct intel_display to PCH macrosJani Nikula1-4/+2
2025-04-10drm/i915: Simplify combo PLL frac w/aVille Syrjälä1-5/+2
2025-04-10drm/i915: Apply the combo PLL frac w/a on DG1Ville Syrjälä1-0/+1
2025-03-25drm/i915: Enable/disable shared dplls just the once for joined pipesVille Syrjälä1-2/+2
2025-03-25drm/i915/pch: convert intel_pch_refclk.c to struct intel_displayJani Nikula1-4/+2
2025-02-19drm/i915/display: Allow display PHYs to reset power stateMika Kahola1-0/+3
2025-02-12drm/i915/dpll: Replace all other leftover drm_i915_privateSuraj Kandpal1-51/+49
2025-02-12drm/i915/dpll: Accept intel_display as argument for shared_dpll_initSuraj Kandpal1-24/+25
2025-02-12drm/i915/dpll: Use intel_display for update_refclk hookSuraj Kandpal1-16/+16
2025-02-12drm/i915/dpll: Use intel_display for asserting pllSuraj Kandpal1-6/+3
2025-02-12drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooksSuraj Kandpal1-403/+389
2025-02-12drm/i915/dpll: Use intel_display for dpll dump and compare hw stateSuraj Kandpal1-8/+8
2025-02-12drm/i915/dpll: Change param to intel_display in for_each_shared_dpllSuraj Kandpal1-9/+15
2025-02-11drm/i915: Convert intel_display_power_{get,put}*() to intel_displayVille Syrjälä1-21/+34
2025-01-23drm/i915/display: fix typos in i915/display filesNitin Gote1-1/+1
2024-12-16drm/i915/uncore: add to_intel_uncore() and use itJani Nikula1-0/+1
2024-10-30drm/i915/dpio: convert to struct intel_displayJani Nikula1-2/+4
2024-10-29drm/i915/display: convert I915_STATE_WARN() to struct intel_displayJani Nikula1-43/+47
2024-08-16drm/i915/hti: convert to struct intel_displayJani Nikula1-1/+2
2024-07-30drm/i915: Fix possible int overflow in skl_ddi_calculate_wrpll()Nikita Zhandarovich1-3/+3
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä1-0/+1
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä1-1/+1
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä1-63/+120
2024-04-17drm/i915: Pass the PLL hw_state to pll->enable()Ville Syrjälä1-32/+37
2024-04-17drm/i915: Introduce some local PLL state variablesVille Syrjälä1-40/+50
2024-04-17drm/i915: Rename PLL hw_state variables/argumentsVille Syrjälä1-111/+112
2024-03-21drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula1-15/+7
2024-03-18drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed()Jonathon Hall1-1/+1
2024-03-15drm/i915: Convert intel_dpll_dump_hw_state() to drm_printerVille Syrjälä1-58/+47
2024-02-15drm/i915: Add PLL .compare_hw_state() vfuncVille Syrjälä1-0/+95
2024-02-15drm/i915: Reuse ibx_dump_hw_state() for gmch platformsVille Syrjälä1-7/+1
2024-01-26drm/i915: Convert PLL flags to booleansVille Syrjälä1-10/+9
2024-01-26drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLsVille Syrjälä1-4/+19
2024-01-26drm/i915: Include the PLL name in the debug messagesVille Syrjälä1-19/+20
2024-01-23drm/i915: Try to preserve the current shared_dpll for fastset on type-c portsVille Syrjälä1-1/+7
generated by cgit v1.2.3 (git 2.39.0) at 2025-11-02 10:37:00 +0300