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path: root/drivers/gpu/drm/amd
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2022-05-11drm/amdkfd: Update event_interrupt_isr_v11 returnGraham Sider1-4/+5
Add amdgpu_no_queue_eviction_on_vm_fault condition to event_interrupt_isr_v11 return. If no queue eviction on vm fault specified, function should return false for client/source ids specifying vm fault. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amdgpu: Disable SDMA WPTR_POLL_ENABLE for sdma_v6_0Graham Sider1-1/+1
WPTR_POLL_ENABLE = 1 was kept to support legacy doorbell programming in SimNow environment. Disable for real hardware. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: enable gfxoff control on smu_v13_0_7Kenneth Feng3-0/+5
enable gfxoff control interface on smu_v13_0_7 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: disable ac/dc on smu_v13_0_7Kenneth Feng1-1/+0
temporarily disable ac/dc on smu_v13_0_7 due to the force clock issue. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: disable the gfxoff feature temporarily for SMU 13.0.0Evan Quan1-0/+2
There is a known "sdma busy" issue with gfxoff enabled. Let's disable the gfxoff feature temporarily until that issue is fixed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: enable FCLK DPM support for SMU 13.0.0Evan Quan1-2/+0
With PMFW 78.35.0, the FCLK DPM is ready to go on SMU 13.0.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: correct the way for retrieving current fclk frequencyEvan Quan1-1/+1
Instead of using AverageFclkFrequencyPostDs/AverageFclkFrequencyPreDs, we turn to target clock frequency(CurrClock[PPCLK_FCLK]). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: correct the way for retrieving current uclk frequencyEvan Quan1-1/+1
There is some problem with average frequency reading for now. So, we switch to the target frequency reading. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: correct the check for current link statusEvan Quan1-2/+3
The output from metrics table for current link status changed. We need to update our driver accordingly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: enable UCLK DPM for SMU 13.0.0Evan Quan1-1/+1
Enable SMU 13.0.0 UCLK DPM. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: enable BACO support for SMU 13.0.0Evan Quan3-0/+93
Enable SMU 13.0.0 BACO support. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amd/pm: enable lclk dpm/ds and BACO features for SMU 13.0.0Evan Quan1-0/+7
Enable those features supported by latest PMFW 78.34.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amdgpu: add sysfs to shows psp vbflash statusLikun Gao3-2/+47
Add new sysfs interface to shows the status of psp vbflash status. V2: rename the sysfs interface, and set more return value. (0: not start; 1: in progress; MBX115 value when vbflash finish) V3: warning fixes Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-11drm/amdgpu/psp: Add vbflash sysfs interface supportLikun Gao4-0/+134
Add sysfs interface to copy VBIOS. v2: squash in fix for proper vmalloc API (Alex) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/psp: Add VBIOS flash handlerAndrey Grodzovsky2-1/+78
Add psp vbflash function for psp v13. v2: fix warnings Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amd/psp: Add C2P registers to mp_13_0_2 headerAndrey Grodzovsky2-0/+120
Add additional registers. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdkfd: Return true/false (not 1/0) from bool functionsYang Li1-3/+3
Return boolean values ("true" or "false") instead of 1 or 0 from bool functions. This fixes the following warnings from coccicheck: ./drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c:244:9-10: WARNING: return of 0/1 in function 'event_interrupt_isr_v11' with return type bool Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/gfx11: remove unneeded semicolonYang Li1-1/+1
Eliminate the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1222:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/vcn4: replace ip based software ring decode with common vcn ↵James Zhu1-11/+9
software ring decode Replace ip based software ring decode with common vcn software ring decode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/vcn3: replace ip based software ring decode with common vcn ↵James Zhu2-83/+9
software ring decode Replace ip based software ring decode with common vcn software ring decode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/vcn: add common vcn sofware ring decodeJames Zhu3-0/+130
Add common vcn sofware ring decode. v2: fixed compiling error Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systemsRichard Gong1-1/+16
Active State Power Management (ASPM) feature is enabled since kernel 5.14. There are some AMD Volcanic Islands (VI) GFX cards, such as the WX3200 and RX640, that do not work with ASPM-enabled Intel Alder Lake based systems. Using these GFX cards as video/display output, Intel Alder Lake based systems will freeze after suspend/resume. The issue was originally reported on one system (Dell Precision 3660 with BIOS version 0.14.81), but was later confirmed to affect at least 4 pre-production Alder Lake based systems. Add an extra check to disable ASPM on Intel Alder Lake based systems with the problematic AMD Volcanic Islands GFX cards. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885 Signed-off-by: Richard Gong <richard.gong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: nuke dynamic gfx scratch reg allocationChristian König8-226/+43
It's over a decade ago that this was actually used for more than ring and IB tests. Just use the static register directly where needed and nuke the now useless infrastructure. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: simplify nv and soc21 read_register functionsAlex Deucher2-6/+6
Check of the base offset for the IP exists rather than explicitly checking for how many instances of a particular IP there are. This is what soc15.c already does. Expand this to nv.c and soc21.c. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: flush delete wq after wait fenceYiqing Yao1-4/+5
[why] lru_list not empty warning in sw fini during repeated device bind unbind. There should be a amdgpu_fence_wait_empty() before the flush_delayed_work() call as Christian suggested. [how] Move to do flush_delayed_work for ttm bo delayed delete wq after fence_driver_hw_fini. Tested by: Yiqing Yao <yiqing.yao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yiqing Yao <yiqing.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amd/display: undo clearing of z10 related function pointersEric Yang1-5/+0
[Why] Z10 and S0i3 have some shared path. Previous code clean up , incorrectly removed these pointers, which breaks s0i3 restore [How] Do not clear the function pointers based on Z10 disable. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systemsRichard Gong1-1/+16
Active State Power Management (ASPM) feature is enabled since kernel 5.14. There are some AMD Volcanic Islands (VI) GFX cards, such as the WX3200 and RX640, that do not work with ASPM-enabled Intel Alder Lake based systems. Using these GFX cards as video/display output, Intel Alder Lake based systems will freeze after suspend/resume. The issue was originally reported on one system (Dell Precision 3660 with BIOS version 0.14.81), but was later confirmed to affect at least 4 pre-production Alder Lake based systems. Add an extra check to disable ASPM on Intel Alder Lake based systems with the problematic AMD Volcanic Islands GFX cards. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885 Signed-off-by: Richard Gong <richard.gong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-05-06drm/amdgpu/discovery: enable mes support for GC v11.0.1Huang Rui1-0/+1
GC v11.0.1 is using MES v11, so add IP block. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: enable gfx v11 for GC 11.0.1Huang Rui1-0/+1
Enable gfx v11 for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: enable imu firmware for GC 11.0.1Huang Rui1-0/+1
The GC 11.0.1 needs load IMU to power up the GFX before loads GFX firmware. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdkfd: add GC 11.0.1 KFD supportHuang Rui2-0/+8
Add initial support for GC 11.0.1 in KFD compute driver. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add GC v11.0.1 into mes v11Huang Rui1-0/+2
Add GC v11.0.1 support into mes v11. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add gfx support for GC 11.0.1Huang Rui1-0/+36
Add GC 11.0.1 gfx support to gfx11 implementation. v2: squash in golden regs Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: set flag for GC 11.0.1Alex Deucher1-0/+1
Set the APU flag appropriately for GC 11.0.1. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: set GC 11.0.1 familyHuang Rui1-0/+3
Add GC 11.0.1 family support. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: enable sdma v6 for SDMA 6.0.1Huang Rui1-0/+1
Enable sdma (system dma) v6 for SDMA 6.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add sdma support for sdma 6.0.1Huang Rui1-0/+1
Add sdma 6.0.1 support to sdma6 implementation. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: add PSP v13.0.4 into the IP discovery listXiaojian Du1-0/+1
This patch will add PSP v13.0.4 into the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: enable ih v6 for OSS 6.0.1Huang Rui1-0/+1
Enable ih (interrupt handler) v6 for OSS 6.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: enable gmc v11 for GC 11.0.1Huang Rui1-0/+1
Enable gmc (graphic memory controller) v11 for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add gmc v11 support for GC 11.0.1Huang Rui1-0/+1
Add gmc v11 support for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: enable soc21 common for GC 11.0.1Huang Rui1-0/+1
Enable soc21 common for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add soc21 common ip block support for GC 11.0.1Huang Rui1-0/+5
Add common soc21 ip block support for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add mmhub support for MMHUB 3.0.1Huang Rui1-0/+1
Add the mmhub support for MMHUB 3.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu/discovery: add HDP v5.2.1 into the IP discovery listXiaojian Du1-0/+4
This patch is to add HDP v5.2.1 in the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add the files of HDP v5.2 blockXiaojian Du3-1/+77
This patch is to add the files of HDP v5.2 block. HDP (Host Data Port) is the IP which handles host access to VRAM via the PCI BAR. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add hdp v5_2_1 ip headersHuang Rui2-0/+901
Add hdp v5.2.1 offset and shift mask ip header files. v2: squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/admgpu/discovery: add NBIO v7.7 into the IP discovery listXiaojian Du1-0/+5
This patch is to add NBIO v7.7 into the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add the files of NBIO v7.7 blockXiaojian Du3-1/+275
This patch is to add the files of NBIO v7.7 block. NBIO (New Bus IO) is the block which handles the GPU interface to the PCIe bus. v2: squash in register name fix (Xiaojian) Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-06drm/amdgpu: add pcie port function helpers for SOC21Xiaojian Du1-0/+2
These helpers will be used on NBIO v7.7.0. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 13:58:22 +0300