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2016-05-11drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2)Alex Deucher6-27/+52
When this flag is set, we program the hardware to execute the flip during horizontal blank (i.e. for the next scanline) instead of during vertical blank (i.e. for the next frame). Ported from radeon commit: drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC v2: drop DAL change for upstream Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu/dce11: don't share PLLs on PolarisAlex Deucher1-4/+0
They are part of the phy so you can't share them. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: Drop unused parameter for *get_sleep_divider_id_from_clockNils Wallménius3-10/+8
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: Simplify calculation in *get_sleep_divider_id_from_clockNils Wallménius5-10/+5
a / (1 << b) is equivalent to a >> b for unsigned values Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: Use max macro in *get_sleep_divider_id_from_clockNils Wallménius4-8/+4
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amd/powerplay: Use defined constants for minium engine clockNils Wallménius2-3/+4
Replacing magic numbers in calculation of sleep divider id for fiji and polaris. Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: add missing licenses on a couple of filesAlex Deucher2-0/+45
Noticed by n1s on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: fetch cu_info once at initAlex Deucher9-46/+25
Fetch this info once at init and just store the results for future requests. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amd: cleanup remaining spaces and tabs v2Christian König23-56/+56
This is the result of running the following commands: find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \; v2: drop changes to DAL and internal headers Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: remove define for reserved client IDChristian König2-2/+1
Just set it to zero instead. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: remove owner cleanup v2Christian König1-13/+0
The client ID is now unique, so no need to resert the owner fields any more. v2: remove unused variables as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: make the VMID owner always 64bitChristian König2-3/+3
Otherwise we could (in theory) run into problems on 32bit systems. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: two minor 80 char fixesChristian König3-8/+12
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: hdp flush&inval should always doMonk Liu1-7/+5
This fixes Tonga vm-fault issue when running disaster (a multiple context GL heavy tests), We should always flush & invalidate hdp no matter vm used or not. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-05-11drm/amd/amdgpu: Enable CG for UVD6 on CarrizoTom St Denis1-1/+2
Tested via vdpau/mpv. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: add pipeline sync for compute jobChunming Zhou1-1/+2
hardware ring is async processed, the job is executed in parallel. In some case, this will result vm fault, like jobs with different vmids. This works around a CPC hw issue which will eventually be fixed in fw. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: keep vm in job instead of ib (v2)Monk Liu12-30/+25
ib.vm is a legacy way to get vm, after scheduler implemented vm should be get from job, and all ibs from one job share the same vm, no need to keep ib.vm just move vm field to job. this patch as well add job as paramter to ib_schedule so it can get vm from job->vm. v2: agd: sqaush in: drm/amdgpu: check if ring emit_vm_flush exists in vm flush No vm flush on engines that don't support VM. bug: https://bugs.freedesktop.org/show_bug.cgi?id=95195 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: make vmid owner be client_idChunming Zhou1-3/+3
Using the pointer is not adequate. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: add client id for every vmChunming Zhou2-0/+8
This adds a unique id for each vm client so we can properly track them. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: fix wrong release of vmid ownerChunming Zhou1-5/+9
The release of the vmid owner was not handled correctly. We need to take the lock and walk the lru list. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-09Merge tag 'v4.6-rc7' into drm-nextDave Airlie13-20/+46
Merge this back as we've built up a fair few conflicts, and I have some newer trees to pull in.
2016-05-09drm/amdgpu: fix build on aarch64.Dave Airlie1-0/+1
Same fix went in previously for some other files. Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-06Merge branch 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie126-3067/+60709
into drm-next This is the first big radeon/amdgpu pull request for 4.7. Highlights: - Polaris support in amdgpu Current display stack on par with other asics, for advanced features DAL is required Power management support Support for GFX, Compute, SDMA, UVD, VCE - VCE and UVD init/fini cleanup in radeon - GPUVM improvements - Scheduler improvements - Clockgating improvements - Powerplay improvements - TTM changes to support driver specific LRU update mechanism - Radeon support for new Mesa features - ASYNC pageflip support for radeon - Lots of bug fixes and code cleanups * 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux: (180 commits) drm/amdgpu: Replace rcu_assign_pointer() with RCU_INIT_POINTER() drm/amdgpu: use drm_mode_vrefresh() rather than mode->vrefresh drm/amdgpu/uvd6: add bypass support for fiji (v3) drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) drm/powerplay: add missing clockgating callback for tonga drm/amdgpu: Constify some tables drm/amd/powerplay: Delete dead struct declaration drm/amd/powerplay/hwmgr: don't add invalid voltage drm/amd/powerplay/hwmgr: prevent VDDC from exceeding 2V MAINTAINERS: Remove unneded wildcard for the Radeon/AMDGPU drivers drm/radeon: add cayman VM support for append packet. drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie drm/amd/amdgpu: Drop print_status callbacks. drm/amd/powerplay: revise reading/writing pptable on Polaris10 drm/amd/powerplay: revise reading/writing pptable on Tonga drm/amd/powerplay: revise reading/writing pptable on Fiji drm/amd/powerplay: revise caching the soft pptable and add it's size drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) drm/amd/powerplay: fix fan speed percent setting error on Polaris10 drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris ...
2016-05-05drm/amdgpu: Replace rcu_assign_pointer() with RCU_INIT_POINTER()Muhammad Falak R Wani1-1/+1
The rcu_assign_pointer() ensures that the initialization of a structure is carried out before storing a pointer to that structre. It is always safe to use RCU_INIT_POINTER() to NULL a pointer, instead of rcu_assign_pointer(). This results in slightly smaller/faster code. The following semantic patch was used: <smpl> @@ @@ - rcu_assign_pointer + RCU_INIT_POINTER (..., NULL) </smpl> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Muhammad Falak R Wani <falakreyaz@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amdgpu: use drm_mode_vrefresh() rather than mode->vrefreshAlex Deucher1-1/+1
This is a port of radeon commit: 3d2d98ee1af0cf6eebfbd6bff4c17d3601ac1284 drm/radeon: use drm_mode_vrefresh() rather than mode->vrefresh to amdgpu. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-05-05drm/amdgpu/uvd6: add bypass support for fiji (v3)Alex Deucher1-0/+19
Handle uvd clock bypass settings as part of clockgating setup. v2: fix gate logic v3: fix header include Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)Alex Deucher1-2/+9
Need to call the IP cg callbacks. v2: fix gate logic Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/powerplay: add missing clockgating callback for tongaAlex Deucher1-0/+1
Without this clockgating is not enabled. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amdgpu: Constify some tablesNils Wallménius6-33/+36
Some more tables with constant data were added with the polaris support v2: missed a few Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: Delete dead struct declarationNils Wallménius1-1/+0
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay/hwmgr: don't add invalid voltageMoritz Kühner1-26/+28
if atomctrl_get_voltage_evv_on_sclk returns non zero (fail) in the expansion of the PP_ASSERT_WITH_CODE macro the continue will actually do nothing (The macro uses a do ... while(0) as scope, which eats the continue). Based on the code I don't think this was the intent. Unfortunately fixing this requires rewriting the control flow and removing the macros. v2: added signed of by fixed error message print v3: agd: drop DRM_ERROR Signed-off-by: Moritz Kühner <kuehner.moritz@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay/hwmgr: prevent VDDC from exceeding 2VMoritz Kühner1-2/+1
If the tonga gpu is controlled by SVID2 tonga_get_evv_voltage will only print an error if the voltage exceeds 2V although a comment clearly states that it needs be less than 2V. v2: added signed of by Signed-off-by: Moritz Kühner <kuehner.moritz@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/amdgpu: Add debugfs entries for smc/didt/pcieTom St Denis2-9/+223
This adds 3 new files that can be read/written to access indirect GPU registers. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/amdgpu: Drop print_status callbacks.Tom St Denis31-1776/+0
First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: revise reading/writing pptable on Polaris10Eric Huang2-4/+30
Change the way we store pptables in the driver to better facilitate eventual runtime updates for debugging. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: revise reading/writing pptable on TongaEric Huang2-12/+27
Change the way we store pptables in the driver to better facilitate eventual runtime updates for debugging. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: revise reading/writing pptable on FijiEric Huang2-7/+37
Change the way we store pptables in the driver to better facilitate eventual runtime updates for debugging. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: revise caching the soft pptable and add it's sizeEric Huang2-6/+10
This fixes a bug in the pptable access interface that could lead to a crash. Check the pointer before using it. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)Eric Huang8-34/+81
Allows you to force multiple levels rather than just one via the new sysfs interrface. v2: squash in: drm/amd/powerplay: ensure clock level set by user is valid. From Rex. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: fix fan speed percent setting error on Polaris10Eric Huang1-2/+2
The logic was reversed. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: fix bug dpm can't work when resume back on PolarisEric Huang1-0/+5
Need to initialize the values to 0 since they get or'ed with additional values. If the initialization is missing, on resume, they may end up with a combination of stale data and new data. Fixes dpm on resume. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: fix some initialize error on polaris10.Rex Zhu1-4/+1
1. don't enable SclkThrottleLowNotification, it's not supported. 2. Set missing mclk_dpm0_activity_target Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: return 0 when interface not implement on some asic.Rex Zhu1-56/+113
Don't fail if certain optional interface callbacks are missing. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amdgpu: fix memory leak in CGS (FW info)Mykola Lysenko1-34/+36
Previously requested FW pointer should not be overwritten on a subsequent call. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: update vce power gate state for baffin.Rex Zhu1-0/+2
Forgot to save the current gate state so we don't know what the current state is if we try and gate/ungate the block. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: Fix a bug for enabling ACDC gpio interruptEric Huang1-4/+7
Only enable it if it's supported rather than unconitionally. Signed-off-by: Eric Yang <eric.yang2@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: fix issue that get wrong reference clock value.Rex Zhu1-1/+1
use wrong parameter to compute the reference clock. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: parameter updates according to SMC.Rex Zhu2-20/+22
Update to latest changes for SMC team. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: add fan control mode interface for baffinRex Zhu1-0/+26
Add interface for manual fan control. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-05drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2)Rex Zhu2-13/+83
Sync up with internal updates. v2: squash in: drm/amd/powerplay: set revert flag for enable thermal protect. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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