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path: root/drivers/gpu/drm/amd
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2018-03-08drm/amd/display: Make create_stream_for_sink more consistentHarry Wentland1-28/+25
We've got a helper function to call dc_create_stream_for_sink and one other place that calls it directly. Make sure we call the helper functions always since we need to update a bunch of things in stream and don't want to miss that. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Don't block dual-link DVI modesHarry Wentland1-2/+1
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Don't allow dual-link DVI on all ASICs.Harry Wentland6-2/+10
Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Pass signal directly to enable_tmds_outputHarry Wentland5-18/+9
This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Remove unnecessary fail labels in create_stream_for_sinkHarry Wentland1-9/+5
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Move MAX_TMDS_CLOCK define to headerHarry Wentland4-15/+5
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Fix FBC topology changeRoman Li1-4/+19
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Fix topology change issue in MST rehookJerry (Fangzhi) Zuo1-0/+6
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)Shirish S1-0/+28
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. This change leads to BUG hit while performing atomic commit on amd driver. As a fix this patch ensures that we disable the CRTC's with NULL FB by returning -EINVAL and hence triggering fall back to the old behavior and turning off the crtc in atomic_remove_fb(). V2: Added error check for plane_state and removed sanity check for crtc. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu/dce6: Use DRM_DEBUG instead of DRM_INFO for HPD IRQ infoMichel Dänzer1-1/+1
For consistency with other DCE generations. HPD IRQs appear to be working fine. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Default HDMI6G support to true. Log VBIOS table error.Harry Wentland1-3/+13
There have been many reports of Ellesmere and Baffin systems not being able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN bit from VBIOS table. Windows seems to not have this issue. On some systems we fail to the encoder cap info from VBIOS. In that case we should default to enabling HDMI6G support. This was tested by dwagner on https://bugs.freedesktop.org/show_bug.cgi?id=102820 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-08drm/amd/display: update plane params before validationShirish S1-0/+3
This patch updates the dc's plane state with the parameters set by the user side. This is needed to validate the plane capabilities with the parameters user space wants to set. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: validate plane in dce110 for scalingShirish S1-0/+11
CZ & ST support uptil a limit 2:1 downscaling, this patch adds validate_plane hook, that shall be used to validate the plane attributes sent by the user space based on dce110 capabilities. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: defer modeset check in dm_update_planes_stateShirish S1-2/+4
amdgpu_dm_atomic_check() is used to validate the entire configuration of planes and crtc's that the user space wants to commit. However amdgpu_dm_atomic_check() depends upon DRM_MODE_ATOMIC_ALLOW_MODESET flag else its mostly dummy. Its not mandatory for the user space to set DRM_MODE_ATOMIC_ALLOW_MODESET, and in general its not set either along with DRM_MODE_ATOMIC_TEST_ONLY. Considering its importantance, this patch defers the allow_modeset check in dm_update_planes_state(), so that there shall be scope to validate the configuration sent from user space, without impacting the population of dc/dm related data structures. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: Don't blow up if TG is NULL in dce110_vblank_setHarry Wentland1-1/+1
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: Notify sbios device ready before send requestRex Zhu1-0/+3
it is required if a platform supports PCIe root complex core voltage reduction. After receiving this notification, SBIOS can apply default PCIe root complex power policy. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-08drm/amdgpu: fix KV harvestingAlex Deucher1-28/+2
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-08drm/amdgpu:Always save uvd vcpu_bo in VM ModeJames Zhu1-5/+8
When UVD is in VM mode, there is not uvd handle exchanged, uvd.handles are always 0. So vcpu_bo always need save, Otherwise amdgpu driver will fail during suspend/resume. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-08drm/amdgpu:Correct max uvd handlesJames Zhu1-1/+1
Max uvd handles should use adev->uvd.max_handles instead of AMDGPU_MAX_UVD_HANDLES here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-08drm/amdgpu: replace iova debugfs file with iomem (v3)Tom St Denis1-21/+81
This allows access to pages allocated through the driver with optional IOMMU mapping. v2: Fix number of bytes copied and add write method v3: drop check for kmap return Original-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/display: validate plane format on primary planeShirish S1-0/+7
In dce110, the plane configuration is such that plane 0 or the primary plane should be rendered with only RGB data. This patch adds the validation to ensure that no video data is rendered on plane 0. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: Clean sdma wptr register when only enable wptr pollingEmily Deng1-2/+5
The sdma wptr polling memory is not fast enough, then the sdma wptr register will be random, and not equal to sdma rptr, which will cause sdma engine hang when load driver, so clean up the sdma wptr directly to fix this issue. v2:add comment above the code and correct coding style Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis2-0/+32808
These are required by umr to properly parse bitfield offsets. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: give warning before sleep in kiq_r/wregMonk Liu1-0/+7
to catch error that may schedule in atomic context early on Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: further mitigate workaround for i915Christian König1-3/+9
Disable the workaround on imported BOs as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: drop gtt->adevChristian König1-5/+5
We can use ttm->bdev instead. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: add amdgpu_evict_gtt debugfs entryChristian König1-1/+12
Allow evicting all BOs from the GTT domain. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/pp: Add #ifdef checks for CONFIG_ACPIRex Zhu2-0/+4
Fix compiling error when CONFIG_ACPI not enabled. Change-Id: I5f901adbc799c10b30e5ea79f8f44760e749fae1 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
2018-03-08drm/amd/pp: fix "Delete the wrapper layer of smu_allocate/free_memory"Christian König2-2/+2
For amdgpu_bo_create_kernel to work the handle must be NULL initialized, otherwise we only try to pin and map the BO. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/pp: Drop wrapper functions for upper/lower_32_bitsRex Zhu5-33/+28
replace smu_upper_32_bits/smu_lower_32_bits with the standard kernel macros Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amdgpu: Delete cgs wrapper functions for gpu memory managerRex Zhu2-246/+0
delete those cgs interfaces: amdgpu_cgs_alloc_gpu_mem amdgpu_cgs_free_gpu_mem amdgpu_cgs_gmap_gpu_mem amdgpu_cgs_gunmap_gpu_mem amdgpu_cgs_kmap_gpu_mem amdgpu_cgs_kunmap_gpu_mem Reviewed-by: Alex Deucher <alexdeucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/pp: Delete the wrapper layer of smu_allocate/free_memoryRex Zhu10-301/+195
use amdgpu_bo_create/free_kernel instand. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/pp: Remove cgs wrapper function for temperature updateRex Zhu3-20/+3
Reviewed-by: Alex Deucher <alexdeucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08Revert "drm/amd/pp: Add a pp feature mask bit for AutoWattman feature"Rex Zhu1-1/+0
This reverts commit e429ea87b2939c4cce1b439baf6d76535a0767f2. Implement Workload Aware Dynamic power management instand of AutoWattman feature in linux. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-08drm/amd/pp: Add auto power profilng switch based on workloads (v2)Rex Zhu9-37/+66
Add power profiling mode dynamic switch based on the workloads. Currently, support Cumpute, VR, Video, 3D,power saving with Cumpute have highest prority, power saving have lowest prority. in manual dpm mode, driver will stop auto switch, just save the client's requests. user can set power profiling mode through sysfs. when exit manual dpm mode, driver will response the client's requests. switch based on the client's prority. v2: squash in fixes from Rex Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Revert gfx/compute profile switch sysfsRex Zhu18-998/+0
The gfx/compute profiling mode switch is only for internally test. Not a complete solution and unexpectly upstream. so revert it. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Fix sclk in highest two levels when compute on smu7Rex Zhu1-0/+21
Compute workload tends to be "bursty", Only tune the behavior of nature dpm don't work well for most of such workloads. From test results, Fix sclk in highest two levels can get better performance. so add min sclk setting into the default cumpute workload policy on smu7. user still can change sclk range through sysfs pp_dpm_sclk for better perf/watt. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Implement get/set_power_profile_mode on smu7Rex Zhu1-0/+143
It show what parameters can be configured to tune the behavior of natural dpm for perf/watt on smu7. user can select the mode per workload, but even the default per workload settings are not bulletproof. user can configure custom settings per different use case for better perf or better perf/watt. cat pp_power_profile_mode NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING: 10 0 30 - - - 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM: 0 0 0 0 0 0 * CURRENT: 0 100 30 0 100 10 Under manual dpm level, user can echo "0/1/2/3/4">pp_power_profile_mode to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE mode. echo "5 * * * * * * * *">pp_power_profile_mode to set custom settings. "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL" if the parameter enable_sclk/enable_mclk is true, driver will update the following parameters to dpm table. if false, ignore the following parameters. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Implement update_dpm_settings on CIRex Zhu1-0/+97
use SW method to update DPM settings by updating SRAM directly on CI. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Implement update_dpm_settings on TongaRex Zhu1-0/+97
use SW method to update DPM settings by updating SRAM directly on Tonga. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-06drm/amd/pp: Implement update_dpm_settings on FijiRex Zhu1-0/+97
use SW method to update DPM settings by updating SRAM directly on Fiji. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amd/display: Fix active dongle hotplugRoman Li1-0/+4
Clean fake sink flag after detecting link on downstream port. Fixing display light-up after "hot-unplug&plug again" downstream of an active dongle. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amdgpu: used cached pcie gen info for SI (v2)Alex Deucher2-49/+23
Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-05drm/amd/amdgpu: Mask rptr as well in ring debugfsTom St Denis1-1/+1
The read/write pointers on sdma4 devices increment beyond the ring size and should be masked. Tested on my Ryzen 2400G. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amdgpu: fix KV harvestingAlex Deucher1-28/+2
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-03-05drm/amd/pp: Implement update_dpm_settings on PolarisRex Zhu1-0/+97
v2: lock dpm level when update pptable by SW method use SW method to update DPM settings by updating SRAM directly on Polaris. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amd/pp: Add a helper to set field in u32Rex Zhu2-0/+18
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amd/pp: Add common interface in smu for update dpm settingRex Zhu3-0/+10
it is used for adjust part of dpm settigs per workloads to change the natural dpm behavior for better perf or perf/watt. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amd/pp: Add PCC feature support on VegaRex Zhu3-0/+36
This features controls vega peak current protection to allow for a wider compatibility with power supplies. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-05drm/amd/pp: Export new smu message for PCC feature on Vega10Rex Zhu1-2/+2
used to set PccThrottleLevel and PccResidencyThreshold Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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