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path: root/drivers/gpu/drm/amd
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2017-03-30drm/amdgpu: gb_addr_config structAndrey Grodzovsky1-0/+10
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: use new flag to handle different firmware loading methodHuang Rui10-20/+90
This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add clinetid definition for vega10ken1-2/+40
Signed-off-by: ken <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add vega10 chip nameKen Wang2-0/+2
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add common soc15 headersKen Wang3-0/+377
These are used by various IP modules. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add SDMA 4.0 packet headerAlex Deucher1-0/+3335
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add gfx9 clearstate headerAlex Deucher1-0/+941
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd: Add MQD structs for GFX V9Felix Kuehling1-0/+675
This header defines the gfx v9 MEC structures. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the VCE 4.0 register headersAlex Deucher3-0/+818
These are the Video Compression Engine registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the UVD 7.0 register headersAlex Deucher3-0/+1160
These are the Unifed Video Decoder registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add THM 9.0 register headersAlex Deucher3-0/+1871
These are the THerMal control registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add SMUIO 9.0 register headersAlex Deucher3-0/+533
These are the System Managment Unit IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add SDMA 4.0 register headersAlex Deucher6-0/+5316
These are the System DMA register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add OSSSYS 4.0 register headersAlex Deucher3-0/+1699
These are the OS Services register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add NBIO 6.1 register headersAlex Deucher3-0/+159873
These are the Bus IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add NBIF 6.1 register headersAlex Deucher3-0/+13240
These are the Bus InterFace registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add MP 9.0 register headersAlex Deucher3-0/+2180
MP is the system management controller on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the MMHUB 1.0 register headersAlex Deucher3-0/+13105
Add the MultiMedia Hub registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the HDP 4.0 register headersAlex Deucher3-0/+927
These are the Host Data Path registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the GC 9.0 register headersAlex Deucher3-0/+40971
Add the Graphics Core register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add the DCE 12.0 register headersAlex Deucher3-0/+92697
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add ATHUB 1.0 register headersAlex Deucher3-0/+2739
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add vega10_enum.hAlex Deucher1-0/+22531
This adds the register bitfield enums for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add soc15ip.hAlex Deucher1-0/+1343
This header defines the IP layout for soc15 based SoCs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add basic support for atomfirmware.h (v3)Alex Deucher5-13/+172
This adds basic support for asics that use atomfirmware.h to define their vbios tables. v2: rebase v3: squash in num scratch reg fix Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: move atom scratch setup into amdgpu_atombios.cAlex Deucher5-28/+32
There will be a slightly different version for atomfirmware. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30amdgpu: detect if we are using atomfirmware or atombios for vbios (v2)Alex Deucher2-7/+24
Supposedly atomfirmware rom header is 3.3 atombios is 1.1. v2: rebased on newer kernel Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the new atomfirmware interface headerAlex Deucher3-0/+2720
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freedNicolai Hähnle4-9/+19
We will add the fence to freed buffer objects in a later commit, to ensure that the underlying memory can only be re-used after all references in page tables have been cleared. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/powerplay: restore disabling power containment on Fiji (v2)Eric Huang1-0/+7
Power containment will degrade performance in some compute tests. Restore disabling it as before code refining in powerplay. v2: only in the compute profile Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: further KIQ parameter cleanupAlex Deucher1-13/+11
The ring structure already has what we need. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: store the eop gpu addr in the ring structureAlex Deucher2-8/+7
Avoids passing around additional parameters during setup. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: reduce the functon params for mpq setupAlex Deucher1-18/+14
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: reserve kiq eop object before unmapping itAlex Deucher1-0/+4
It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: fold loops in kiq_resume()Alex Deucher1-4/+0
No need to loop through the compute queues twice. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: test KIQ before compute ringsAlex Deucher1-6/+7
If KIQ isn't working, the compute rings won't work either. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: reserve mqd objects before mapping themAlex Deucher1-11/+21
It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: rename some functionsAlex Deucher1-6/+6
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: whitespace cleanupAlex Deucher1-6/+5
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: load mc firware in driver for Polaris.Rex Zhu1-6/+84
load mc ucode in driver if VBIOS not loaded a full version of MC ucode, Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: jimqu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: fix duplicated codeChunming Zhou1-4/+0
it could come from branch merge. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: enable gfx/system/vce clockgating on Polars12.Rex Zhu2-1/+20
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/powerplay: add a new register define for APU in VI.Rex Zhu4-4/+15
the ixcurrent_pg_status addr is different between APU and DGPU. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: enable GFX/UVD/VCE PG for BristolEric Huang1-1/+4
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/amdgpu: Set VCE/UVD off during late initTom St Denis1-0/+4
Forces VCE/UVD off during late init to ensure they're powered off correctly during boot. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: remove redundant outer loop and remove commented out codeColin Ian King1-20/+7
The outer loop is redundant and can be removed as it is doing nothing useful. Also remove some commented out code that is not being used. Detected by CoverityScan, CID#1402073 Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/sched: revise priority numberChunming Zhou2-6/+7
big number is to high priority. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: bump version for PRT supportAlex Deucher1-1/+2
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: fix before and after mapping judgement for replace mappingJunwei Zhang1-4/+6
If the before mapping is 1 page size, so its start and last will be same. Thus below condition will become false, then to free the before mapping. > if (before->it.start != before->it.last) But in this case, we need the before mapping of 1 page size. So does after mapping. Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add a VM mapping replace operation v2Christian König3-1/+82
Add a new operation to replace mappings in a VM with a new one. v2: Fix Jerry's comment, separate out clear operation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 12:55:10 +0300