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path: root/drivers/gpu/drm/amd/include
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2017-05-25drm/amdgpu: add register headers for VCN 1.0Alex Deucher3-0/+1886
Add registers for Video Controller Next 1.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for THM 10.0Alex Deucher3-0/+1283
Add registers for THerMal control 10.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for SDMA 4.1Alex Deucher3-0/+2359
Add registers for SDMA 4.1 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for NBIO 7.0Alex Deucher3-0/+138450
Add registers for NBIO 7.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for MP 10.0Alex Deucher3-0/+1404
Add registers for MP 10.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for MMHUB 9.1Alex Deucher3-0/+12817
Add registers for the MultiMedia Hub 9.1 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for GC 9.1Alex Deucher3-0/+42687
Registers for Graphics Controller 9.1 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add register headers for DCN 1.0Alex Deucher3-0/+76391
Registers for Display Controller Next 1.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-25drm/amdgpu: add DP audio support for si dce6 (v3)Xiaojie Yuan1-0/+2
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-10drm/amdgpu: add amd fan ctrl mode enums.Rex Zhu1-0/+6
Add common fan enums that can be used for both powerplay and dpm. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-29drm/amdgpu: remove unused and mostly unimplemented CGS functions v2Christian König1-270/+0
Those functions are all unused and some not even implemented. v2: keep cgs_get_pci_resource, it is used by the ACP driver. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add interrupt entries for CRTC_VERTICAL_INTERRUPT0.Andrey Grodzovsky1-0/+99
This used by DAL ISR logic for VBLANK handling. Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx9: impl gfx9 meta data emitXiangliang Yu1-0/+68
Insert ce meta prior to cntx_cntl and de follow it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd: add structures for display/powerplay interfaceEric Huang1-0/+83
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add PSP driver for vega10 (v2)Huang Rui1-0/+1
PSP is responsible for firmware loading on SOC-15 asics. v2: fix memory leak (Ken) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add GMC 9.0 support (v2)Alex Xie1-0/+2
On SOC-15 parts, the GMC (Graphics Memory Controller) consists of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce). v2: drop sdma from Makefile, fix duplicate return statement. Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add vega10 chip nameKen Wang1-0/+1
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd: Add MQD structs for GFX V9Felix Kuehling1-0/+675
This header defines the gfx v9 MEC structures. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the VCE 4.0 register headersAlex Deucher3-0/+818
These are the Video Compression Engine registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the UVD 7.0 register headersAlex Deucher3-0/+1160
These are the Unifed Video Decoder registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add THM 9.0 register headersAlex Deucher3-0/+1871
These are the THerMal control registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add SMUIO 9.0 register headersAlex Deucher3-0/+533
These are the System Managment Unit IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add SDMA 4.0 register headersAlex Deucher6-0/+5316
These are the System DMA register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add OSSSYS 4.0 register headersAlex Deucher3-0/+1699
These are the OS Services register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add NBIO 6.1 register headersAlex Deucher3-0/+159873
These are the Bus IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add NBIF 6.1 register headersAlex Deucher3-0/+13240
These are the Bus InterFace registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add MP 9.0 register headersAlex Deucher3-0/+2180
MP is the system management controller on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the MMHUB 1.0 register headersAlex Deucher3-0/+13105
Add the MultiMedia Hub registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the HDP 4.0 register headersAlex Deucher3-0/+927
These are the Host Data Path registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the GC 9.0 register headersAlex Deucher3-0/+40971
Add the Graphics Core register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add the DCE 12.0 register headersAlex Deucher3-0/+92697
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: Add ATHUB 1.0 register headersAlex Deucher3-0/+2739
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add vega10_enum.hAlex Deucher1-0/+22531
This adds the register bitfield enums for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add soc15ip.hAlex Deucher1-0/+1343
This header defines the IP layout for soc15 based SoCs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add the new atomfirmware interface headerAlex Deucher3-0/+2720
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/powerplay: add a new register define for APU in VI.Rex Zhu2-0/+3
the ixcurrent_pg_status addr is different between APU and DGPU. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add new ATIF ACPI methodAlex Deucher1-0/+12
Used for fetching external GPU information. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add DF MGCG flagHuang Rui1-0/+1
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: add DRM MGCG headerHuang Rui1-0/+1
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher1-9/+10
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.hXiangliang Yu1-0/+106
Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>Joe Perches1-2/+2
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amdgpu: implement PRT for GFX6 v2Christian König1-0/+4
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-30drm/amd/amdgpu: add power profile sysfs entryEric Huang1-0/+14
Add the sysfs entries pp_gfx_power_profile and pp_compute_power_profile which give user a way to set power profile through parameters minimum sclk, minimum mclk, activity threshold, up hysteresis and down hysteresis only when the entry power_dpm_force_performance_level is in default value "auto". It is read and write. Example: echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile cat /sys/class/drm/card0/device/pp_*_power_profile 500 800 20 0 5 Note: first parameter is sclk in MHz, second is mclk in MHz, third is activity threshold in percentage, fourth is up hysteresis in ms and fifth is down hysteresis in ms. echo set > /sys/class/drm/card0/device/pp_*_power_profile To set power profile state if it exists. echo reset > /sys/class/drm/card0/device/pp_*_power_profile To restore default state and clear previous setting. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-28scripts/spelling.txt: add "aligment" pattern and fix typo instancesMasahiro Yamada1-3/+3
Fix typos and add the following to the scripts/spelling.txt: aligment||alignment I did not touch the "N_BYTE_ALIGMENT" macro in drivers/net/wireless/realtek/rtlwifi/wifi.h to avoid unpredictable impact. I fixed "_aligment_handler" in arch/openrisc/kernel/entry.S because it is surrounded by #if 0 ... #endif. It is surely safe and I confirmed "_alignment_handler" is correct. I also fixed the "controler" I found in the same hunk in arch/openrisc/kernel/head.S. Link: http://lkml.kernel.org/r/1481573103-11329-8-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-02-28scripts/spelling.txt: add "swith" pattern and fix typo instancesMasahiro Yamada1-1/+1
Fix typos and add the following to the scripts/spelling.txt: swith||switch swithable||switchable swithed||switched swithing||switching While we are here, fix the "update" to "updates" in the touched hunk in drivers/net/wireless/marvell/mwifiex/wmm.c. Link: http://lkml.kernel.org/r/1481573103-11329-2-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-02-16drm/amd/powerplay: add kicker flag into smumgrHuang Rui1-0/+1
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13drm/amdgpu: read hw register to check pg status.Rex Zhu7-1/+12
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-09drm/amdgpu: add current_pg_status register define for smu7.1Rex Zhu1-0/+1
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: move misc si headers into amdgpuAlex Deucher2-3402/+0
Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 21:33:51 +0300