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2023-08-30drm/amd/display: switch to new ODM policy for windowed MPO ODM supportWenjing Liu1-19/+65
We need to align windowed MPO ODM support on DCN3x with new ODM policy. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: use new pipe allocation interface in dcn32 fpuWenjing Liu1-149/+339
This commit implements a new pipe resource allocation logic for DCN32 when windowed ODM MPO flag is set to enable testing. By default the flag is not set. It will be toggled on after we complete testing. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add more pipe resource interfacesWenjing Liu18-464/+659
Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add new resource interfaces to update odm mpc slice countWenjing Liu2-6/+432
Define two new interfaces to update mpc and odm slice count. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add new resource interface for acquiring sec opp heads and ↵Wenjing Liu5-0/+134
release pipe [why] We need a new algorithm for acquiring secondary opp heads for ODM combine in dcn32 and a release pipe interface to properly release pipe resources. [how] add two new interfaces in DCN specific resource file. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: rename function to add otg master for streamWenjing Liu1-44/+69
We are renaming acquire first free pipe to add otg master pipe for stream because the former name doesn't indicate that it acquires the first free pipe to use as an otg master pipe. This could cause coding errors if someone uses it to acquire a different pipe type. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add comments to add plane functionsWenjing Liu1-21/+70
Adding detail comments describing the problem we are solving with add plane function. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Add DPIA Link Encoder Assignment FixMustapha Ghaddar5-6/+58
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: update blank state on ODM changesWenjing Liu1-27/+9
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: stable@vger.kernel.org Fixes: 7fbf451e7639 ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Add smu write msg id fail retry processFudong Wang1-4/+16
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: stable@vger.kernel.org # 6.1+ Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Fudong Wang <fudong.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Add support for 1080p SubVP to reduce idle powerEthan Bitnun4-3/+50
- Override the det to adjust microschedule timings allow for 1080p configs with SubVP - To lower unnecessary risk, we prevent multi 1080p configs from using SubVP, as multi 1080p already has low idle power. - Count the number of streams to verify that we are in a SubVP config before overriding Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Ethan Bitnun <ethan.bitnun@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30Partially revert "drm/amd/display: update add plane to context logic with a ↵Wenjing Liu1-4/+114
new algorithm" This partially reverts commit 460ea8980511 ("drm/amd/display: update add plane to context logic with a new algorithm"). The new secondary pipe allocation logic triggers an issue with a specific hardware state transition and causes a frame of corruption when toggling between windowed MPO and ODM desktop only mode. Ideally hwss is supposed to handle this scenario. We are temporarily reverting the logic and investigate the root cause why this transition would cause corruptions. Fixes: 460ea8980511 ("drm/amd/display: update add plane to context logic with a new algorithm") Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: register edp_backlight_control() for DCN301Hamza Mahfooz1-0/+1
As made mention of in commit 099303e9a9bd ("drm/amd/display: eDP intermittent black screen during PnP"), we need to turn off the display's backlight before powering off an eDP display. Not doing so will result in undefined behaviour according to the eDP spec. So, set DCN301's edp_backlight_control() function pointer to dce110_edp_backlight_control(). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765 Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit") Suggested-by: Swapnil Patel <swapnil.patel@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: 3.2.248Aric Cyr1-1/+1
This version brings along following fixes: - Ensure FS is enabled before sending request to DMUB for FS changes - Add check for PMFW hard min request complete - Save addr update in scratch before flip - Fix static screen detection setting - Write flip addr to scratch reg for subvp - set minimum of VBlank_nom - Correct unit conversion for vstartup - Roll back unit correction - Enable runtime register offset init for DCN32 DMUB - Refactor edp power control - PQ regamma end point - PQ tail accuracy - Expose mall capability Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: [FW Promotion] Release 0.0.180.0Anthony Koo1-5/+0
- Remove unused flag otg_powered_down Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Anthony Koo <anthony.koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: ensure FS is enabled before sending request to DMUB for FS ↵Samson Tam1-2/+4
changes [Why] ignore_msa_timing_param indicates FS is capable but not necessarily enabled [How] add check for either allow_freesync or vrr_active_variable to confirm FS is enabled Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add check for PMFW hard min request completeSamson Tam2-3/+162
[Why] When we issue hard min request to PMFW, the ack back does not guarantee the request has been fulfilled. [How] Add new PMFW message to check if the hard min request has been completed. Returned bit mask indicates which clock requests are completed. Check PMFW version before using message Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Save addr update in scratch before flipAlvin Lee1-5/+5
[Why & How] Fix a minor sequencing issue where the address update for a subvp flip should be saved in scratch registers before the actual flip Reviewed-by: Austin Zheng <austin.zheng@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: fix static screen detection settingSungHuai Wang6-4/+23
[WHY] OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3, but we still follow DCN2 to apply setting for OTG_STATIC_SCREEN_EVENT_MASK. [How] Add new function to apply correct settings for DCN3 series. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: SungHuai Wang <danny.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: fix mode scaling (RMX_.*)Hamza Mahfooz1-1/+1
As made mention of in commit 4a2df0d1f28e ("drm/amd/display: Fixed non-native modes not lighting up"), we shouldn't call drm_mode_set_crtcinfo() once the crtc timings have been decided. Since, it can cause settings to be unintentionally overwritten. So, since dm_state is never NULL now, we can use old_stream to determine if we should call drm_mode_set_crtcinfo() because we only need to set the crtc timing parameters for entirely new streams. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Fixes: bd49f19039c1 ("drm/amd/display: Always set crtcinfo from create_stream_for_sink") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Write flip addr to scratch reg for subvpAlvin Lee11-1/+134
[Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: set minimum of VBlank_nomChunTao Tso1-1/+20
[Why] If VBlank_nom is too small, it will cause VStartUP_Start smaller than VBackPorch + VSync width which is an invalid case for VStartUP_Start and where to send AS-SDP. [How] Setup a minimum value to VBlank_nom Reviewed-by: Reza Amini <reza.amini@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: ChunTao Tso <chuntao.tso@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Correct unit conversion for vstartupReza Amini1-1/+24
[why] vstartup is calculated to be a large number. it works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [how] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Reza Amini <reza.amini@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Roll back unit correctionOvidiu Bunea1-24/+1
[why] This Unit correction exposes a Replay corruption. [how] This reverts commit: commit dbd29029c7b5 ("drm/amd/display: Correct unit conversion for vstartup") Roll back unit conversion until Replay can fix their corruption. Fixes: dbd29029c7b5 ("drm/amd/display: Correct unit conversion for vstartup") Reviewed-by: Reza Amini <reza.amini@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Enable runtime register offset init for DCN32 DMUBAurabindo Pillai5-20/+36
[Why&How] DMUB subsystem was continuing to use compile time offset calculation for register access. Switch this to runtime calculation to stay consistent with rest of DC code. To enable this, an additional interface init_reg_offsets() are added to DMUB's hw_funcs struct. Asics with runtime register offset calculation enabled shall populate this hook with a fn pointer that will invoke the necessary macros to calculate the offset. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Refactor edp power controlIan Chen11-9/+66
[Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: PQ regamma end pointKrunoslav Kovac1-6/+109
[WHY & HOW] PQ has a fixed range of 0-10,000 nits. Using 1=80 nits normalization, PQ should map to 1.0 for X=125.0 HW LUT used for interpolation does not have X=125 so it's interpolated. However, we cap Y to 1 for all X>=125. The closest larger HW point is 128. What we want is Y(128) such that interpolation through 125 gives 1.0. Such value is ~1.00256. Another change is to hardcode PQ table, we pretty much always have 1=80 normalization so the table can be static. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: PQ tail accuracyKrunoslav Kovac2-88/+33
[WHY & HOW] HW LUTs changed slightly in DCN3: 256 base+slope pairs were replaced by 257 bases. Code was still calculating all 256 base+slope and then creating 257th pt as last base + last slope. This was done in wrong format, and then "fixed" it by making the last two points the same thus making the last slope=0. However, this also created some precision problems near the end that are not visible but they do show up with capture cards. Solution is to calculate 257 and remove deltas since we no longer have those HW registers. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Expose mall capabilityAurabindo Pillai1-0/+19
[Why&How] Export a debugfs file to report whether MALL cache is supported by the asic or not. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Fix useless else if in display_mode_vba_util_32.cSrinivasan Shanmugam1-4/+0
The assignment of the else if and else branches is the same, so the else if here is redundant, hence removed it. Fixes the below: drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c:4664:8-10: WARNING: possible condition with no effect (if == else) Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Fix unnecessary conversion to bool in 'amdgpu_dm_setup_replay'Srinivasan Shanmugam1-2/+2
Fixes the following coccicheck: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:94:102-107: WARNING: conversion to bool not needed here drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:102:72-77: WARNING: conversion to bool not needed here Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: Enable Replay for static screen use casesBhawanpreet Lakha2-1/+30
- Setup replay config on device init. - Enable replay if feature is enabled (prioritize replay over PSR, since it can be enabled in more usecases) - Add debug masks to enable replay on supported ASICs Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-24BackMerge tag 'v6.5-rc7' into drm-nextDave Airlie1-0/+12
Linux 6.5-rc7 This is needed for the CI stuff and the msm pull has fixes in it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2023-08-16Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0""Alex Deucher1-1/+1
This reverts commit 27dd79c00aeab36cd7542c7a4481a32549038659. It appears MPC_SPLIT_DYNAMIC still causes problems with multiple displays on DCN2.0 hardware. Switch back to MPC_SPLIT_AVOID_MULT_DISP. This increases power usage with multiple displays, but avoids hangs. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2475 Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.4.x
2023-08-16Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0""Alex Deucher1-1/+1
This reverts commit 27dd79c00aeab36cd7542c7a4481a32549038659. It appears MPC_SPLIT_DYNAMIC still causes problems with multiple displays on DCN2.0 hardware. Switch back to MPC_SPLIT_AVOID_MULT_DISP. This increases power usage with multiple displays, but avoids hangs. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2475 Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Handle Replay related hpd irqBhawanpreet Lakha1-0/+66
Handle replay related hpd irqs Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Update adaptive sync infopackets for replayBhawanpreet Lakha2-2/+7
Update infopackets for replay Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Promote DAL to 3.2.247Aric Cyr1-1/+1
This version brings along following fixes: - Improve power saving feature - Clean up for code clarity - Fix crashing bug - Fix pipe allocation for older ASIC - Fix for gamut remap - Fix 8K 60Hz display in test cases - Fix bug in clock gating - Improve DP2 compliance Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: [FW Promotion] Release 0.0.179.0Anthony Koo1-0/+4
- Add defines to specify new PHY power states Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Anthony Koo <anthony.koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Replace ternary operator with min() in ↵Srinivasan Shanmugam1-1/+1
'dm_helpers_parse_edid_caps' Fixes the following coccicheck: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:120:41-42: WARNING opportunity for min() Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: enable low power mode for VGA memoryAurabindo Pillai1-0/+5
[Why] When unused, all memory blocks should be put in a low power state [How] Check the value of enable_mem_low_power.bits.vga and set corresponding bit in the hardware register Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Add some missing register definitionsAurabindo Pillai1-29/+40
[Why&How] Add some missing register definitions and rearrange some others to maintain consistency with related definitions. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: avoid crash and add z8_marks related in dmlCharlene Liu4-5/+8
[why] add dml1 used calculate_wm_and_dlg function pointer check to prevent crash. add z8 watermarks to struct for later asic use Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: implement pipe type definition and adding accessorsWenjing Liu19-185/+375
[why] There is a lack of encapsulation of pipe connection representation in pipe context. This has caused many challenging bugs and coding errors with repeated logic to identify the same pipe type. [how] Formally define pipe types and provide getters to identify a pipe type and find a pipe based on specific requirements. Update existing logic in non dcn specific files and dcn32 and future versions to use the new accessors. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Enable 8k60hz mode on single displayNicholas Susanto1-1/+3
[Why] 8k60hz compliace test failing because we restrict it single memory channels. Workaround by not restricting it on single displays. [How] Adding an additional check to DCN314 to restrict 8k60hz mode if it has more than 1 display connected. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: fix incorrect stream_res allocation for older ASICWenjing Liu1-14/+13
[why] There is a recent work for developing a new pipe resource allocation policy used for new ASIC. The new code change needs to modify asic independent pipe resource allocation flow and hook up the new allocation policy in asic dependent layer. Unfortunately this change revealed a hidden bug in the old pipe resource allocation sequence used for older asics. In the older version of acquiring pipe for layer, we are always assigning otg master's opp and tg to the newly allocated secondary dpp pipe. This logic is incorrect when the secodnary dpp pipe is connected to a secondary opp head pipe in ODM combine configuration. Before the recent change, we will overwrite this wrong assignement in asic independent layer again. This covers up the issue. With the recent change, we will no longer cover up this in upper layer and therefore causes wrong tg and opp assignement to the secondary dpp pipe connected to a secondary opp head. [how] Always assign tg and opp from its own opp head instead of otg master. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Gamut remap only changes missedKrunoslav Kovac1-0/+1
[WHY&HOW] If surface format is dynamically changed within app without changing timing / whole plane, we don't reprogram gamut remap matrix. Issue example: Linear FP16 scRGB going to PQ+BT.2020 monitor. Remap = scRGB->BT.2020 App switches swapchain format to 10-bit PQ+BT.2020. SW calculates correctly that new Remap = bypass (in=-out=BT.2020). But update not applied in HW. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: PMFW to wait for DMCUB ack for FPO casesAlvin Lee3-0/+13
[Description] We want PMFW to wait for DMCUB to ACK the MCLK end message for FPO cases as well. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: Enable subvp high refresh up to 175hzAlvin Lee2-3/+4
[Description] Expand the SubVP policy to include up to 175hz displays for better power saving on more display configs. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-16drm/amd/display: disable clock gating logic reversed bug fixMuhammad Ahmed2-4/+4
[Why] disable clock gating logic reversed bug fix Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-28 04:32:30 +0300